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/linux/Documentation/sound/cards/
H A Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
32 (Note: Choosing the 56channel mode for transmission or as
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
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/linux/include/drm/
H A Ddrm_modes.h3 * Copyright © 2007-2008 Dave Airlie
4 * Copyright © 2007-2008 Intel Corporation
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
46 * enum drm_mode_status - hardware support status of a mode
47 * @MODE_OK: Mode OK
50 * @MODE_H_ILLEGAL: mode has illegal horizontal timings
51 * @MODE_V_ILLEGAL: mode has illegal vertical timings
53 * @MODE_NOMODE: no mode with a matching name
54 * @MODE_NO_INTERLACE: interlaced mode not supported
55 * @MODE_NO_DBLESCAN: doublescan mode not supported
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_sync.c1 // SPDX-License-Identifier: MIT
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
32 #include <linux/dma-fence-chain.h>
46 * amdgpu_sync_create - zero init sync object
48 * @sync: sync object to initialize
50 * Just clear the sync object for now.
52 void amdgpu_sync_create(struct amdgpu_sync *sync) in amdgpu_sync_create() argument
54 hash_init(sync->fences); in amdgpu_sync_create()
58 * amdgpu_sync_same_dev - test if fence belong to us
73 ring = container_of(s_fence->sched, struct amdgpu_ring, sched); in amdgpu_sync_same_dev()
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/linux/drivers/tty/serial/
H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
90 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
91 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
93 #define ENT_HM 0x10 /* Enter Hunt Mode */
106 #define SYNC_ENAB 0 /* Sync Modes Enable */
111 #define MONSYNC 0 /* 8 Bit Sync character */
112 #define BISYNC 0x10 /* 16 bit sync character */
113 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
114 #define EXTSYNC 0x30 /* External Sync Mode */
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H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
82 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
83 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
85 #define ENT_HM 0x10 /* Enter Hunt Mode */
98 #define SYNC_ENAB 0 /* Sync Modes Enable */
103 #define MONSYNC 0 /* 8 Bit Sync character */
104 #define BISYNC 0x10 /* 16 bit sync character */
105 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
106 #define EXTSYNC 0x30 /* External Sync Mode */
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H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
109 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
110 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
112 #define ENT_HM 0x10 /* Enter Hunt Mode */
124 #define SYNC_ENAB 0 /* Sync Modes Enable */
130 #define MONSYNC 0 /* 8 Bit Sync character */
131 #define BISYNC 0x10 /* 16 bit sync character */
132 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
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H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
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/linux/tools/testing/selftests/arm64/mte/
H A Dcheck_mmap_options.c1 // SPDX-License-Identifier: GPL-2.0
29 1, 537, 989, 1269, MT_GRANULE_SIZE - 1, MT_GRANULE_SIZE,
30 /* page size - 1*/ 0, /* page_size */ 0, /* page size + 1 */ 0
33 static int check_mte_memory(char *ptr, int size, int mode, int tag_check) in check_mte_memory() argument
35 mte_initialize_current_context(mode, (uintptr_t)ptr, size); in check_mte_memory()
41 mte_initialize_current_context(mode, (uintptr_t)ptr, -UNDERFLOW); in check_mte_memory()
42 memset(ptr - UNDERFLOW, '2', UNDERFLOW); in check_mte_memory()
49 mte_initialize_current_context(mode, (uintptr_t)ptr, size + OVERFLOW); in check_mte_memory()
60 static int check_anonymous_memory_mapping(int mem_type, int mode, int mapping, int tag_check) in check_anonymous_memory_mapping() argument
66 mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); in check_anonymous_memory_mapping()
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H A Dcheck_tags_inclusion.c1 // SPDX-License-Identifier: GPL-2.0
22 static int verify_mte_pointer_validity(char *ptr, int mode) in verify_mte_pointer_validity() argument
24 mte_initialize_current_context(mode, (uintptr_t)ptr, BUFFER_SIZE); in verify_mte_pointer_validity()
29 ksft_print_msg("Unexpected fault recorded for %p-%p in mode %x\n", in verify_mte_pointer_validity()
30 ptr, ptr + BUFFER_SIZE, mode); in verify_mte_pointer_validity()
36 mte_initialize_current_context(mode, (uintptr_t)ptr, BUFFER_SIZE + 1); in verify_mte_pointer_validity()
41 ksft_print_msg("No vali in verify_mte_pointer_validity()
49 check_single_included_tags(int mem_type,int mode) check_single_included_tags() argument
81 check_multiple_included_tags(int mem_type,int mode) check_multiple_included_tags() argument
113 check_all_included_tags(int mem_type,int mode) check_all_included_tags() argument
139 check_none_included_tags(int mem_type,int mode) check_none_included_tags() argument
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H A Dcheck_buffer_fill.c1 // SPDX-License-Identifier: GPL-2.0
17 1, 555, 1033, MT_GRANULE_SIZE - 1, MT_GRANULE_SIZE,
18 /* page size - 1*/ 0, /* page_size */ 0, /* page size + 1 */ 0
28 static int check_buffer_by_byte(int mem_type, int mode) in check_buffer_by_byte() argument
34 mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TAG); in check_buffer_by_byte()
41 mte_initialize_current_context(mode, (uintptr_t)ptr, sizes[i]); in check_buffer_by_byte()
63 static int check_buffer_underflow_by_byte(int mem_type, int mode, in check_buffer_underflow_by_byte() argument
71 mte_switch_mode(mode, MTE_ALLOW_NON_ZERO_TA in check_buffer_underflow_by_byte()
158 check_buffer_overflow_by_byte(int mem_type,int mode,int overflow_range) check_buffer_overflow_by_byte() argument
261 check_buffer_by_block_iterate(int mem_type,int mode,size_t size) check_buffer_by_block_iterate() argument
336 check_buffer_by_block(int mem_type,int mode) check_buffer_by_block() argument
365 check_memory_initial_tags(int mem_type,int mode,int mapping) check_memory_initial_tags() argument
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/linux/drivers/net/hamradio/
H A Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
57 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
58 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
60 #define ENT_HM 0x10 /* Enter Hunt Mode */
72 #define SYNC_ENAB 0 /* Sync Modes Enable */
77 #define MONSYNC 0 /* 8 Bit Sync character */
78 #define BISYNC 0x10 /* 16 bit sync character */
79 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
80 #define EXTSYNC 0x30 /* External Sync Mode */
82 #define X1CLK 0x0 /* x1 clock mode */
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/linux/arch/powerpc/kernel/
H A Dcpu_setup_ppc970.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <asm/asm-offsets.h>
15 /* Do nothing if not running in HV mode */
28 sync
31 sync
34 sync
37 sync
41 li r3,0x1200 /* enable i-fetch cacheability */
50 sync
71 /* Do nothing if not running in HV mode */
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H A Didle_6xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * it will have PLL 1 set to low speed mode (used during NAP/DOZE).
9 * be done to check a runtime var (a bit like powersave-nap)
18 #include <asm/asm-offsets.h>
19 #include <asm/feature-fixups.h>
25 * Make sure no rest of NAP mode remains in HID0, save default
73 /* Now check if user or arch enabled NAP mode */
84 /* Some pre-nap cleanups needed on some CPUs */
96 sync
98 sync
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/linux/Documentation/networking/
H A Dipvs-sysctl.rst1 .. SPDX-License-Identifier: GPL-2.0
4 IPvs-sysctl
10 am_droprate - INTEGER
13 It sets the always mode drop rate, which is used in the mode 3
16 amemthresh - INTEGER
20 used in the automatic modes of defense. When there is no
25 backup_only - BOOLEAN
26 - 0 - disabled (default)
27 - not 0 - enabled
30 in backup mode to avoid packet loops for DR/TUN methods.
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/linux/include/uapi/linux/
H A Dnet_tstamp.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
38 SOF_TIMESTAMPING_MASK = (SOF_TIMESTAMPING_LAST - 1) |
53 * struct so_timestamping - SO_TIMESTAMPING parameter
65 * struct hwtstamp_config - %SIOCGHWTSTAMP and %SIOCSHWTSTAMP parameter
74 * the driver may use a more general filter mode. In this case
75 * @rx_filter will indicate the actual mode on return.
83 /* possible values for hwtstamp_config->flags */
95 HWTSTAMP_FLAG_MASK = (HWTSTAMP_FLAG_LAST - 1) | HWTSTAMP_FLAG_LAST
98 /* possible values for hwtstamp_config->tx_type */
101 * No outgoing packet will need hardware time stamping;
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H A Dfb.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
24 /* 0x4607-0x460B are defined below */
52 #define FB_AUX_TEXT_SVGA_GROUP 8 /* 8-15: SVGA tileblit compatible modes */
54 #define FB_AUX_TEXT_SVGA_STEP2 8 /* SVGA text mode: text, attr */
55 #define FB_AUX_TEXT_SVGA_STEP4 9 /* SVGA text mode: text, attr, 2 reserved bytes */
56 #define FB_AUX_TEXT_SVGA_STEP8 10 /* SVGA text mode: text, attr, 6 reserved bytes */
57 #define FB_AUX_TEXT_SVGA_STEP16 11 /* SVGA text mode: text, attr, 14 reserved bytes */
72 #define FB_ACCEL_NONE 0 /* no hardware accelerator */
140 #define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */
142 #define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */
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/linux/drivers/gpu/drm/mcde/
H A Dmcde_display.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 #include <linux/dma-buf.h>
11 #include <linux/media-bus-format.h>
80 mispp = readl(mcde->regs + MCDE_MISPP); in mcde_display_irq()
81 misovl = readl(mcde->regs + MCDE_MISOVL); in mcde_display_irq()
82 mischnl = readl(mcde->regs + MCDE_MISCHNL); in mcde_display_irq()
92 if (!mcde->dpi_output && mcde_dsi_irq(mcde->mdsi)) { in mcde_display_irq()
96 * In oneshot mode we do not send continuous updates in mcde_display_irq()
101 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) { in mcde_display_irq()
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H A Dmcde_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
46 const struct drm_display_mode *mode; member
73 d = host_to_mcde_dsi(mdsi->host); in mcde_dsi_irq()
75 dev_dbg(d->dev, "%s called\n", __func__); in mcde_dsi_irq()
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); in mcde_dsi_irq()
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
81 dev_dbg(d->dev, "direct command write completed\n"); in mcde_dsi_irq()
84 dev_dbg(d->dev, "direct command TE received\n"); in mcde_dsi_irq()
87 dev_err(d->dev, "direct command ACK ERR received\n"); in mcde_dsi_irq()
89 dev_err(d->dev, "direct command read ERR received\n"); in mcde_dsi_irq()
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/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
41 * - Render Target Cache Flush Enable ([12] of DW1)
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/linux/tools/power/pm-graph/config/
H A Dexample.cfg9 # sudo ./sleepgraph.py -config config/example.cfg
14 # ---- General Options ----
20 # Suspend Mode
22 mode: mem
26 output-dir: suspend-{hostname}-{date}-{time}
44 # Sync filesystem before suspend
45 # run sync before the test, minimizes sys_sync call time (default: false)
46 sync: true
49 # Enable/disable runtime suspend for all devices, restore all after test (default: no-action)
53 # Switch the display on/off for the test using xset (default: no-action)
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/linux/drivers/gpu/drm/i915/display/
H A Ddvo_ns2501.c21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
73 #define NS2501_C0_ENABLE (1<<0) /* enable the DVO sync in general */
79 * Register 41 is somehow related to the sync register and sync
101 #define NS2501_REG1C 0x1c /* low-part of the second register */
102 #define NS2501_REG1D 0x1d /* high-part of the second register */
107 * 2^16/control-value. The low-byte comes first.
109 #define NS2501_REG10 0x10 /* low-byte vertical scaler */
110 #define NS2501_REG11 0x11 /* high-byte vertical scaler */
111 #define NS2501_REGB8 0xb8 /* low-byte horizontal scaler */
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/linux/drivers/video/fbdev/
H A Dfm2fb.c2 * linux/drivers/video/fm2fb.c -- BSC FrameMaster II/Rainbow II frame buffer
5 * Copyright (C) 1998 Steffen A. Mork (linux-dev@morknet.de)
35 * - PAL/NTSC
36 * - interlaced/non interlaced
37 * - composite sync/sync/sync over green
40 * - 768x576 (PAL)
41 * - 768x480 (NTSC)
60 * 2 4 0=normal mode as jumpered via JP8/1=complement mode
67 * JP1 interlace selection (1-2 non interlaced/2-3 interlaced)
70 * JP4 modulate composite sync on green output (1-2 composite
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/linux/drivers/media/dvb-frontends/
H A Dcx24110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 cx24110 - Single Chip Satellite Channel Receiver driver module
5 Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on
48 {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
52 {0x0b,0x01}, /* set output clock in gapped mode, start signal low
54 {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
55 {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
63 {0x17,0x04}, /* @ time window allowed for the RS to sync */
74 /* leave front-end AGC parameters at default values */
82 {0x41,0x00}, /* @ MSB of front-end derotator frequency */
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/linux/drivers/net/ethernet/sfc/siena/
H A Dptp.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2011-2013 Solarflare Communications Inc.
143 #define MC_NANOSECOND_MASK ((1 << MC_NANOSECOND_BITS) - 1)
144 #define MC_SECOND_MASK ((1 << (32 - MC_NANOSECOND_BITS)) - 1)
146 /* Maximum parts-per-billion adjustment that is acceptable */
161 * struct efx_ptp_match - Matching structure, stored in sk_buff's cb area.
165 * @state: The state of the packet - whether it is ready for processing or
166 * whether that is of no interest.
175 * struct efx_ptp_event_rx - A PTP receive event (from MC)
191 * struct efx_ptp_timeset - Synchronisation between host and MC
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dpi.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/media-bus-format.h>
16 #include <linux/soc/mediatek/mtk-mmsys.h>
75 struct drm_display_mode mode; member
120 * struct mtk_dpi_conf - Configuration of mediatek dpi.
133 * (no shift).
134 * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
163 u32 tmp = readl(dpi->regs + offset) & ~mask; in mtk_dpi_mask()
166 writel(tmp, dpi->regs + offset); in mtk_dpi_mask()
185 struct mtk_dpi_sync_param *sync) in mtk_dpi_config_hsync() argument
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