Lines Matching +full:no +full:- +full:sync +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0+
46 const struct drm_display_mode *mode;
73 d = host_to_mcde_dsi(mdsi->host);
75 dev_dbg(d->dev, "%s called\n", __func__);
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG);
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val);
81 dev_dbg(d->dev, "direct command write completed\n");
84 dev_dbg(d->dev, "direct command TE received\n");
87 dev_err(d->dev, "direct command ACK ERR received\n");
89 dev_err(d->dev, "direct command read ERR received\n");
91 writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR);
93 val = readl(d->regs + DSI_CMD_MODE_STS_FLAG);
95 dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val);
98 dev_dbg(d->dev, "CMD mode no TE\n");
101 dev_dbg(d->dev, "CMD mode TE miss\n");
103 dev_err(d->dev, "CMD mode SD1 underrun\n");
105 dev_err(d->dev, "CMD mode SD2 underrun\n");
107 dev_err(d->dev, "CMD mode unwanted RD\n");
108 writel(val, d->regs + DSI_CMD_MODE_STS_CLR);
110 val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG);
112 dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val);
113 writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR);
115 val = readl(d->regs + DSI_TG_STS_FLAG);
117 dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val);
118 writel(val, d->regs + DSI_TG_STS_CLR);
120 val = readl(d->regs + DSI_VID_MODE_STS_FLAG);
122 dev_dbg(d->dev, "DSI_VID_MODE_STS_FLAG = %08x\n", val);
124 dev_dbg(d->dev, "VID mode VSG running\n");
126 dev_err(d->dev, "VID mode missing data\n");
128 dev_err(d->dev, "VID mode missing HSYNC\n");
130 dev_err(d->dev, "VID mode missing VSYNC\n");
132 dev_err(d->dev, "VID mode less bytes than expected between two HSYNC\n");
134 dev_err(d->dev, "VID mode less lines than expected between two VSYNC\n");
138 dev_err(d->dev, "VID mode read/write error\n");
140 dev_err(d->dev, "VID mode received packets differ from expected size\n");
142 dev_err(d->dev, "VID mode VSG in recovery mode\n");
143 writel(val, d->regs + DSI_VID_MODE_STS_CLR);
150 d->mcde->mdsi = d->mdsi;
154 * currently we just support video or command mode depending
155 * on the type of display. Video mode defaults to using the
161 * single frame on-demand updates with DRM for command mode
164 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)
165 d->mcde->flow_mode = MCDE_VIDEO_FORMATTER_FLOW;
167 d->mcde->flow_mode = MCDE_COMMAND_TE_FLOW;
175 if (mdsi->lanes < 1 || mdsi->lanes > 2) {
177 return -EINVAL;
180 dev_info(d->dev, "attached DSI device with %d lanes\n", mdsi->lanes);
182 dev_info(d->dev, "format %08x, %dbpp\n", mdsi->format,
183 mipi_dsi_pixel_format_to_bpp(mdsi->format));
184 dev_info(d->dev, "mode flags: %08lx\n", mdsi->mode_flags);
186 d->mdsi = mdsi;
187 if (d->mcde)
198 d->mdsi = NULL;
199 if (d->mcde)
200 d->mcde->mdsi = NULL;
216 size_t txlen = msg->tx_len;
217 size_t rxlen = msg->rx_len;
222 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
223 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
225 writel(1, d->regs + DSI_DIRECT_CMD_SEND);
228 if (MCDE_DSI_HOST_IS_READ(msg->type)) {
230 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
233 && --loop_counter)
236 dev_err(d->dev, "DSI read timeout!\n");
238 return -ETIME;
242 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) &
244 && --loop_counter)
249 dev_err(d->dev, "DSI write timeout!\n");
250 return -ETIME;
254 val = readl(d->regs + DSI_DIRECT_CMD_STS);
256 dev_err(d->dev, "read completed with error\n");
257 writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT);
258 return -EIO;
262 dev_err(d->dev, "error during transmission: %04x\n",
264 return -EIO;
267 if (!MCDE_DSI_HOST_IS_READ(msg->type)) {
274 u8 *rx = msg->rx_buf;
276 rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY);
278 rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT);
280 dev_err(d->dev, "read error, requested %zd got %d\n",
282 return -EIO;
298 const u8 *tx = msg->tx_buf;
299 size_t txlen = msg->tx_len;
300 size_t rxlen = msg->rx_len;
307 dev_err(d->dev,
309 return -EIO;
312 dev_err(d->dev,
314 return -EIO;
317 dev_dbg(d->dev,
319 msg->channel, txlen, rxlen);
322 if (MCDE_DSI_HOST_IS_READ(msg->type))
333 if (mipi_dsi_packet_format_is_long(msg->type))
338 val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;
339 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
347 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0);
352 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1);
358 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2);
364 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3);
374 dev_err(d->dev, "gave up after %d retries\n", retries);
377 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
378 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
395 d = host_to_mcde_dsi(mdsi->host);
404 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
409 d->regs + DSI_DIRECT_CMD_STS_CLR);
410 val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL);
413 writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL);
415 /* Clear and enable no TE or TE missing status */
418 d->regs + DSI_CMD_MODE_STS_CLR);
419 val = readl(d->regs + DSI_CMD_MODE_STS_CTL);
422 writel(val, d->regs + DSI_CMD_MODE_STS_CTL);
425 writel(1, d->regs + DSI_DIRECT_CMD_SEND);
429 const struct drm_display_mode *mode)
432 u8 cpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format) / 8;
442 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
444 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
448 /* RGB header and pixel mode */
449 switch (d->mdsi->format) {
471 dev_err(d->dev, "unknown pixel mode\n");
478 * During vertical blanking: go to LP mode
487 * During EOL: go to LP mode. If this is not set, the EOL area will be
491 /* Recovery mode 1 */
494 writel(val, d->regs + DSI_VID_MAIN_CTL);
496 /* Vertical frame parameters are pretty straight-forward */
497 val = mode->vdisplay << DSI_VID_VSIZE_VACT_LENGTH_SHIFT;
499 val |= (mode->vsync_start - mode->vdisplay)
501 /* vertical sync active */
502 val |= (mode->vsync_end - mode->vsync_start)
505 val |= (mode->vtotal - mode->vsync_end)
507 writel(val, d->regs + DSI_VID_VSIZE);
511 * horizontal resolution is given in pixels but must be re-calculated
517 * hsa = horizontal sync active in bytes
521 hfp = (mode->hsync_start - mode->hdisplay) * cpp - 6 - 2;
522 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
524 * Use sync pulse for sync: explicit HSA time
528 hbp = (mode->htotal - mode->hsync_end) * cpp - 4 - 6;
534 hsa = (mode->hsync_end - mode->hsync_start) * cpp - 4 - 4 - 6;
537 * Use event for sync: HBP includes both back porch and sync
542 hbp = (mode->htotal - mode->hsync_start) * cpp - 4 - 4 - 6;
543 /* HSA is not present in this mode and set to 0 */
547 dev_info(d->dev, "hfp negative, set to 0\n");
551 dev_info(d->dev, "hbp negative, set to 0\n");
555 dev_info(d->dev, "hsa negative, set to 0\n");
558 dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u bytes\n",
561 /* Frame parameters: horizontal sync active */
567 writel(val, d->regs + DSI_VID_HSIZE1);
570 val = mode->hdisplay * cpp;
571 writel(val, d->regs + DSI_VID_HSIZE2);
572 dev_dbg(d->dev, "RGB length, visible area on a line: %u bytes\n", val);
577 * porches and sync.
580 pclk = DIV_ROUND_UP_ULL(1000000000000, (mode->clock * 1000));
581 dev_dbg(d->dev, "picoseconds between two pixels: %llu\n",
599 bpl = pclk * mode->htotal; /* (1) picoseconds per line */
600 dev_dbg(d->dev, "picoseconds per line: %llu\n", bpl);
602 bpl *= (d->mdsi->hs_rate / 8);
607 bpl *= d->mdsi->lanes;
608 dev_dbg(d->dev,
610 bpl, drm_mode_vrefresh(mode), d->mdsi->hs_rate);
616 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
618 writel(0, d->regs + DSI_VID_BLKSIZE1);
621 * sync area size is in pixels here, but this -6
625 blkline_pck = bpl - (mode->hsync_end - mode->hsync_start) - 6;
627 writel(val, d->regs + DSI_VID_BLKSIZE2);
629 /* Set the sync pulse packet size to 0 (not used) */
630 writel(0, d->regs + DSI_VID_BLKSIZE2);
631 /* Specifying payload size in bytes (-4-6 from manual) */
632 blkline_pck = bpl - 4 - 6;
634 dev_err(d->dev, "blkline_pck too big %d bytes\n",
638 writel(val, d->regs + DSI_VID_BLKSIZE1);
652 if (d->mdsi->lanes == 2 && (hsa & 0x01) && (hfp & 0x01)
653 && (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST))
654 line_duration--;
655 line_duration = DIV_ROUND_CLOSEST(line_duration, d->mdsi->lanes);
656 dev_dbg(d->dev, "line duration %u bytes\n", line_duration);
659 * This is the time to perform LP->HS on D-PHY
665 writel(val, d->regs + DSI_VID_DPHY_TIME);
669 * of the different burst mode settings.
671 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
674 * Packet size at EOL for burst mode, this is only used
681 blkeol_pck = bpl - (mode->htotal * cpp) - 6;
683 dev_err(d->dev, "video block does not fit on line!\n");
684 dev_err(d->dev,
686 bpl, drm_mode_vrefresh(mode));
687 dev_err(d->dev,
690 dev_err(d->dev,
694 dev_dbg(d->dev, "BLKEOL packet: %d bytes\n", blkeol_pck);
696 val = readl(d->regs + DSI_VID_BLKSIZE1);
699 writel(val, d->regs + DSI_VID_BLKSIZE1);
704 writel(val, d->regs + DSI_VID_VCA_SETTING2);
707 * cycles of the BLLP end-of-line (EOL) period for each line if
718 * FIXME: should this also be set up also for non-burst mode
722 d->mdsi->lanes);
723 dev_dbg(d->dev, "BLKEOL duration: %d clock cycles\n",
726 val = readl(d->regs + DSI_VID_PCK_TIME);
730 writel(val, d->regs + DSI_VID_PCK_TIME);
733 val = readl(d->regs + DSI_VID_VCA_SETTING1);
735 val |= (blkeol_pck - 6) <<
737 writel(val, d->regs + DSI_VID_VCA_SETTING1);
741 val = readl(d->regs + DSI_VID_VCA_SETTING2);
743 val |= (blkline_pck - 6) <<
745 writel(val, d->regs + DSI_VID_VCA_SETTING2);
746 dev_dbg(d->dev, "blkline pck: %d bytes\n", blkline_pck - 6);
755 /* No integration mode */
756 writel(0, d->regs + DSI_MCTL_INTEGRATION_MODE);
763 if (!(d->mdsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))
765 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
769 writel(val, d->regs + DSI_CMD_MODE_CTL);
776 hs_freq = clk_get_rate(d->hs_clk);
779 dev_dbg(d->dev, "UI value: %d\n", val);
782 writel(val, d->regs + DSI_MCTL_DPHY_STATIC);
787 * needed, enable switch into ULPM (ultra-low power mode) on
791 if (d->mdsi->lanes == 2)
793 if (!(d->mdsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
798 writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL);
802 writel(val, d->regs + DSI_MCTL_ULPOUT_TIME);
805 d->regs + DSI_DPHY_LANES_TRIM);
811 writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT);
817 if (d->mdsi->lanes == 2)
819 writel(val, d->regs + DSI_MCTL_MAIN_EN);
826 if (d->mdsi->lanes == 2)
828 while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) {
832 dev_warn(d->dev, "DSI lanes did not start up\n");
839 /* Command mode, clear IF1 ID */
840 val = readl(d->regs + DSI_CMD_MODE_CTL);
842 * If we enable low-power mode here,
845 if (d->mdsi->mode_flags & MIPI_DSI_MODE_LPM)
848 writel(val, d->regs + DSI_CMD_MODE_CTL);
852 dev_info(d->dev, "DSI link enabled\n");
867 if (d->mdsi->lp_rate)
868 lp_freq = d->mdsi->lp_rate;
871 if (d->mdsi->hs_rate)
872 hs_freq = d->mdsi->hs_rate;
877 d->lp_freq = clk_round_rate(d->lp_clk, lp_freq);
878 ret = clk_set_rate(d->lp_clk, d->lp_freq);
880 dev_err(d->dev, "failed to set LP clock rate %lu Hz\n",
881 d->lp_freq);
883 d->hs_freq = clk_round_rate(d->hs_clk, hs_freq);
884 ret = clk_set_rate(d->hs_clk, d->hs_freq);
886 dev_err(d->dev, "failed to set HS clock rate %lu Hz\n",
887 d->hs_freq);
890 ret = clk_prepare_enable(d->lp_clk);
892 dev_err(d->dev, "failed to enable LP clock\n");
894 dev_info(d->dev, "DSI LP clock rate %lu Hz\n",
895 d->lp_freq);
896 ret = clk_prepare_enable(d->hs_clk);
898 dev_err(d->dev, "failed to enable HS clock\n");
900 dev_info(d->dev, "DSI HS clock rate %lu Hz\n",
901 d->hs_freq);
905 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
910 /* De-assert RESET again */
911 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
918 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
919 /* Set up the video mode from the DRM mode */
920 mcde_dsi_setup_video_mode(d, d->mode);
922 /* Put IF1 into video mode */
923 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
925 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
927 /* Disable command mode on IF1 */
928 val = readl(d->regs + DSI_CMD_MODE_CTL);
930 writel(val, d->regs + DSI_CMD_MODE_CTL);
933 val = readl(d->regs + DSI_VID_MODE_STS_CTL);
936 writel(val, d->regs + DSI_VID_MODE_STS_CTL);
938 /* Enable video mode */
939 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
941 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
943 /* Command mode, clear IF1 ID */
944 val = readl(d->regs + DSI_CMD_MODE_CTL);
946 * If we enable low-power mode here
949 if (d->mdsi->mode_flags & MIPI_DSI_MODE_LPM)
952 writel(val, d->regs + DSI_CMD_MODE_CTL);
955 dev_info(d->dev, "enabled MCDE DSI master\n");
959 const struct drm_display_mode *mode,
964 if (!d->mdsi) {
965 dev_err(d->dev, "no DSI device attached to encoder!\n");
969 d->mode = mode;
971 dev_info(d->dev, "set DSI master to %dx%d %u Hz %s mode\n",
972 mode->hdisplay, mode->vdisplay, mode->clock * 1000,
973 (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? "VIDEO" : "CMD"
983 * Wait until we get out of command mode
988 while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) {
992 dev_warn(d->dev,
993 "could not get out of command mode\n");
1004 /* Wait until we get out og video mode */
1007 while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) {
1011 dev_warn(d->dev,
1012 "could not get out of video mode\n");
1027 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1028 /* Stop video mode */
1029 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
1031 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
1034 /* Stop command mode */
1045 writel(0, d->regs + DSI_VID_MODE_STS_CTL);
1046 clk_disable_unprepare(d->hs_clk);
1047 clk_disable_unprepare(d->lp_clk);
1055 struct drm_device *drm = bridge->dev;
1058 dev_err(d->dev, "we need atomic updates\n");
1059 return -ENOTSUPP;
1063 return drm_bridge_attach(encoder, d->bridge_out, bridge, flags);
1081 if (!of_get_available_child_count(dev->of_node)) {
1083 d->unused = true;
1086 d->mcde = mcde;
1088 if (d->mdsi)
1092 d->hs_clk = devm_clk_get(dev, "hs");
1093 if (IS_ERR(d->hs_clk)) {
1095 return PTR_ERR(d->hs_clk);
1098 d->lp_clk = devm_clk_get(dev, "lp");
1099 if (IS_ERR(d->lp_clk)) {
1101 return PTR_ERR(d->lp_clk);
1105 for_each_available_child_of_node(dev->of_node, child) {
1116 return -EINVAL;
1128 d->panel = panel;
1131 dev_info(dev, "connected to non-panel bridge (unsupported)\n");
1132 return -ENODEV;
1134 dev_err(dev, "no panel or bridge\n");
1135 return -ENODEV;
1138 d->bridge_out = bridge;
1141 d->bridge.of_node = dev->of_node;
1142 drm_bridge_add(&d->bridge);
1145 mcde->bridge = &d->bridge;
1157 if (d->panel)
1158 drm_panel_bridge_remove(d->bridge_out);
1159 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
1170 struct device *dev = &pdev->dev;
1179 d->dev = dev;
1183 d->prcmu =
1184 syscon_regmap_lookup_by_compatible("stericsson,db8500-prcmu");
1185 if (IS_ERR(d->prcmu)) {
1186 dev_err(dev, "no PRCMU regmap\n");
1187 return PTR_ERR(d->prcmu);
1190 d->regs = devm_platform_ioremap_resource(pdev, 0);
1191 if (IS_ERR(d->regs))
1192 return PTR_ERR(d->regs);
1194 dsi_id = readl(d->regs + DSI_ID_REG);
1197 host = &d->dsi_host;
1198 host->dev = dev;
1199 host->ops = &mcde_dsi_host_ops;
1215 component_del(&pdev->dev, &mcde_dsi_component_ops);
1216 mipi_dsi_host_unregister(&d->dsi_host);
1221 .compatible = "ste,mcde-dsi",
1228 .name = "mcde-dsi",