Lines Matching +full:no +full:- +full:sync +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
82 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
83 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
85 #define ENT_HM 0x10 /* Enter Hunt Mode */
98 #define SYNC_ENAB 0 /* Sync Modes Enable */
103 #define MONSYNC 0 /* 8 Bit Sync character */
104 #define BISYNC 0x10 /* 16 bit sync character */
105 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
106 #define EXTSYNC 0x30 /* External Sync Mode */
108 #define X1CLK 0x0 /* x1 clock mode */
109 #define X16CLK 0x40 /* x16 clock mode */
110 #define X32CLK 0x80 /* x32 clock mode */
111 #define X64CLK 0xC0 /* x64 clock mode */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
145 #define NV 2 /* No Vector */
150 #define NORESET 0 /* No reset on write to R9 */
156 #define BIT6 1 /* 6 bit/8bit sync */
157 #define LOOPMODE 2 /* SDLC Loop mode */
161 #define NRZ 0 /* NRZ mode */
162 #define NRZI 0x20 /* NRZI mode */
167 /* Write Register 11 (Clock Mode control) */
181 #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
193 #define SEARCH 0x20 /* Enter search mode */
198 #define SFMM 0xc0 /* Set FM mode */
199 #define SNRZI 0xe0 /* Set NRZI mode */
206 #define SYNCIE 0x10 /* Sync/hunt IE */
217 #define SYNC 0x10 /* Sync/hunt */ macro
239 /* Read Register 2 (channel b only) - Interrupt vector */
277 #define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
280 #define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
283 #define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
285 sbus_readb(&channel->data); \
287 sbus_readb(&channel->data); \