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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am68-sk-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j721s2.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
14 bootph-all;
20 reserved_memory: reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
27 no-map;
[all …]
H A Dk3-j721e-som-p0.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
15 bootph-all;
21 reserved_memory: reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
29 no-map;
32 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
[all …]
H A Dk3-am642-tqma64xxl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
7 #include "k3-am642.dtsi"
18 /* 1G RAM - default variant */
23 reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
31 no-map;
34 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
[all …]
H A Dk3-am68-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
6 * https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-j721s2.dtsi"
16 compatible = "phytec,am68-phycore-som", "ti,j721s2";
17 model = "PHYTEC phyCORE-AM68x";
30 bootph-all;
33 reserved_memory: reserved-memory {
[all …]
H A Dk3-j721s2-som-p0.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721s2.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
16 bootph-all;
23 reserved_memory: reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
31 no-map;
[all …]
H A Dk3-am64-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
6 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
10 * https://www.phytec.com/product/phycore-am64x
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/net/ti-dp83867.h>
18 model = "PHYTEC phyCORE-AM64x";
19 compatible = "phytec,am64-phycore-som", "ti,am642";
30 bootph-all;
[all …]
H A Dk3-am67a-beagley-ai.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * https://beagley-ai.org/
5 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-j722s.dtsi"
16 compatible = "beagle,am67a-beagley-ai", "ti,j722s";
17 model = "BeagleBoard.org BeagleY-AI";
27 stdout-path = &main_uart0;
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8926-htc-memul.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
11 /delete-node/ &adsp_region;
12 /delete-node/ &mba_region;
13 /delete-node/ &mpss_region;
14 /delete-node/ &smem_region;
19 chassis-type = "handset";
25 gpio-keys {
26 compatible = "gpio-keys";
28 key-power {
[all …]
H A Dqcom-msm8226-samsung-matisse-common.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 * The .dts should first include qcom-msm8226.dtsi or msm8926.dtsi depending on
11 #include <dt-bindings/input/input.h>
14 /delete-node/ &adsp_region;
15 /delete-node/ &mba_region;
16 /delete-node/ &mpss_region;
17 /delete-node/ &smem_region;
27 #address-cells = <1>;
28 #size-cells = <1>;
31 stdout-path = "display0";
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dversal-net-vn-x-b2197-01-revA.dts1 // SPDX-License-Identifier: GPL-2.0
6 * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "versal-net.dtsi"
14 #include "versal-net-clk.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
18 compatible = "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,versal-net";
20 dma-coherent;
39 stdout-path = "serial1:115200n8";
42 reserved-memory {
[all …]
/linux/Documentation/mm/
H A Dhugetlbfs_reserv.rst8 Huge pages as described at Documentation/admin-guide/mm/hugetlbpage.rst are
11 are to be used. If no huge page exists at page fault time, the task is sent
34 This is a global (per-hstate) count of reserved huge pages. Reserved
37 as (``free_huge_pages - resv_huge_pages``).
38 Reserve Map
39 A reserve map is described by the structure::
50 There is one reserve map for each huge page mapping in the system.
65 These are stored in the bottom bits of the reservation map pointer.
80 Reservation Map Location (Private or Shared)
86 semantics of the reservation map is significantly different for the two types
[all …]
/linux/drivers/mtd/maps/
H A Dphysmap-gemini.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cortina Systems Gemini OF physmap add-on
11 #include <linux/mtd/map.h>
18 #include "physmap-gemini.h"
21 * The Flash-relevant parts of the global status register
63 if (IS_ERR(gf->enabled_state)) in gemini_flash_enable_pins()
65 ret = pinctrl_select_state(gf->p, gf->enabled_state); in gemini_flash_enable_pins()
67 dev_err(gf->dev, "failed to enable pins\n"); in gemini_flash_enable_pins()
74 if (IS_ERR(gf->disabled_state)) in gemini_flash_disable_pins()
76 ret = pinctrl_select_state(gf->p, gf->disabled_state); in gemini_flash_disable_pins()
[all …]
/linux/Documentation/core-api/irq/
H A Dirq-domain.rst9 that each one gets assigned non-overlapping allocations of Linux
24 For this reason, we need a mechanism to separate controller-local
29 the controller-local IRQ (hwirq) number into the Linux IRQ number
38 irq_fwspec to hwirq numbers (Device Tree, non-DT firmware node, ACPI
72 it with the hwirq, and calls the :c:member:`irq_domain_ops.map()`
79 - irq_resolve_mapping() returns a pointer to the irq_desc structure
80 for a given domain and hwirq number, and NULL if there was no
82 - irq_find_mapping() returns a Linux IRQ number for a given domain and
83 hwirq number, and 0 if there was no mapping
84 - generic_handle_domain_irq() handles an interrupt described by a
[all …]
/linux/net/netfilter/
H A Dnft_set_pipapo_avx2.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2019-2020 Red Hat GmbH
29 /* Load from memory into YMM register with non-temporal hint ("stream load"),
33 * - loading buckets from lookup tables, as they are not going to be used
36 * - loading the result bitmap from the previous field, as it's never used
75 * nft_pipapo_avx2_prepare() - Prepare before main algorithm body
86 * nft_pipapo_avx2_fill() - Fill a bitmap region with ones
113 *data |= GENMASK(len - 1 + offset, offset); in nft_pipapo_avx2_fill()
118 len -= BITS_PER_LONG - offset; in nft_pipapo_avx2_fill()
122 mask = ~0UL >> (BITS_PER_LONG - len); in nft_pipapo_avx2_fill()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-phycore-rpmsg.dtso1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
10 #include <dt-bindings/clock/imx8mm-clock.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
23 no-map;
28 no-map;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm845-lg-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
16 /delete-node/ &adsp_mem;
17 /delete-node/ &cdsp_mem;
18 /delete-node/ &gpu_mem;
19 /delete-node/ &ipa_fw_mem;
20 /delete-node/ &mba_region;
21 /delete-node/ &mpss_region;
[all …]
H A Dqcm6490-idp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
12 #include <dt-bindings/input/linux-event-codes.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
15 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
22 /delete-node/ &ipa_fw_mem;
23 /delete-node/ &rmtfs_mem;
24 /delete-node/ &adsp_mem;
25 /delete-node/ &cdsp_mem;
[all …]
/linux/arch/arm/boot/dts/airoha/
H A Den7523.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/en7523-clk.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
13 reserved-memory {
14 #address-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp157a-microgea-stm32mp1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
9 compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
16 reserved-memory {
17 #address-cells = <1>;
18 #size-cells = <1>;
22 compatible = "shared-dma-pool";
24 no-map;
28 compatible = "shared-dma-pool";
30 no-map;
[all …]
H A Dste-db8500.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 #include "ste-dbx5x0.dtsi"
8 operating-points = <998400 0
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
23 no-map;
29 no-map;
35 no-map;
49 no-map;
H A Dste-db8520.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 #include "ste-dbx5x0.dtsi"
8 operating-points = <1152000 0
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
23 no-map;
29 no-map;
35 no-map;
49 no-map;
/linux/drivers/iio/adc/
H A Drohm-bd79124.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * https://fscdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bd79124muf-c-e.pdf
15 #include <linux/devm-helpers.h>
30 #include <linux/iio/adc-helpers.h>
99 struct regmap *map; member
203 return regmap_assign_bits(data->map, BD79124_REG_GPO_VAL, BIT(offset), in bd79124gpo_set()
221 ret = regmap_read(data->map, BD79124_REG_PINCFG, &all_gpos); in bd79124gpo_set_multiple()
226 dev_dbg(data->dev, "Invalid mux config. Can't set value.\n"); in bd79124gpo_set_multiple()
228 return -EINVAL; in bd79124gpo_set_multiple()
231 return regmap_update_bits(data->map, BD79124_REG_GPO_VAL, *mask, *bits); in bd79124gpo_set_multiple()
[all …]
/linux/include/linux/mtd/
H A Dcfi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> et al.
14 #include <linux/mtd/map.h>
28 # define cfi_interleave(cfi) ((cfi)->interleave)
40 # define cfi_interleave(cfi) ((cfi)->interleave)
52 # define cfi_interleave(cfi) ((cfi)->interleave)
62 #warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work.
152 /* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */
159 block follows - FIXME - not currently supported */
205 /* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */
[all …]
/linux/Documentation/sound/designs/
H A Dchannel-mapping-api.rst2 ALSA PCM channel-mapping API
11 and the current channel map, also optionally to modify the channel map
14 A channel map is an array of position for each PCM channel.
15 Typically, a stereo PCM stream has a channel map of
17 while a 4.0 surround PCM stream has a channel map of
20 The problem, so far, was that we had no standard channel map
21 explicitly, and applications had no way to know which channel
29 was no way to specify this because of lack of channel map
38 the kernel/user-space ABI perspective. It uses only the existing
46 * name = "Playback Channel Map" or "Capture Channel Map"
[all …]
/linux/drivers/pinctrl/
H A Dpinconf.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
29 const struct pinconf_ops *ops = pctldev->desc->confops; in pinconf_check_ops()
32 if (!ops->pin_config_set && !ops->pin_config_group_set) { in pinconf_check_ops()
33 dev_err(pctldev->dev, in pinconf_check_ops()
35 return -EINVAL; in pinconf_check_ops()
40 int pinconf_validate_map(const struct pinctrl_map *map, int i) in pinconf_validate_map() argument
42 if (!map->data.configs.group_or_pin) { in pinconf_validate_map()
43 pr_err("failed to register map %s (%d): no group/pin given\n", in pinconf_validate_map()
[all …]

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