1*7b776229SDominik Haller// SPDX-License-Identifier: GPL-2.0 2*7b776229SDominik Haller/* 3*7b776229SDominik Haller * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4*7b776229SDominik Haller * Author: Dominik Haller <d.haller@phytec.de> 5*7b776229SDominik Haller */ 6*7b776229SDominik Haller 7*7b776229SDominik Haller/dts-v1/; 8*7b776229SDominik Haller/plugin/; 9*7b776229SDominik Haller 10*7b776229SDominik Haller#include <dt-bindings/clock/imx8mm-clock.h> 11*7b776229SDominik Haller 12*7b776229SDominik Haller&{/} { 13*7b776229SDominik Haller #address-cells = <2>; 14*7b776229SDominik Haller #size-cells = <2>; 15*7b776229SDominik Haller 16*7b776229SDominik Haller reserved-memory { 17*7b776229SDominik Haller #address-cells = <2>; 18*7b776229SDominik Haller #size-cells = <2>; 19*7b776229SDominik Haller ranges; 20*7b776229SDominik Haller 21*7b776229SDominik Haller m4_reserved: m4@80000000 { 22*7b776229SDominik Haller reg = <0 0x80000000 0 0x1000000>; 23*7b776229SDominik Haller no-map; 24*7b776229SDominik Haller }; 25*7b776229SDominik Haller 26*7b776229SDominik Haller vdev0vring0: vdev0vring0@b8000000 { 27*7b776229SDominik Haller reg = <0 0xb8000000 0 0x8000>; 28*7b776229SDominik Haller no-map; 29*7b776229SDominik Haller }; 30*7b776229SDominik Haller 31*7b776229SDominik Haller vdev0vring1: vdev0vring1@b8008000 { 32*7b776229SDominik Haller reg = <0 0xb8008000 0 0x8000>; 33*7b776229SDominik Haller no-map; 34*7b776229SDominik Haller }; 35*7b776229SDominik Haller 36*7b776229SDominik Haller rsc_table: rsc_table@b80ff000 { 37*7b776229SDominik Haller reg = <0 0xb80ff000 0 0x1000>; 38*7b776229SDominik Haller no-map; 39*7b776229SDominik Haller }; 40*7b776229SDominik Haller 41*7b776229SDominik Haller vdevbuffer: vdevbuffer@b8400000 { 42*7b776229SDominik Haller compatible = "shared-dma-pool"; 43*7b776229SDominik Haller reg = <0 0xb8400000 0 0x100000>; 44*7b776229SDominik Haller no-map; 45*7b776229SDominik Haller }; 46*7b776229SDominik Haller }; 47*7b776229SDominik Haller 48*7b776229SDominik Haller core-m4 { 49*7b776229SDominik Haller compatible = "fsl,imx8mm-cm4"; 50*7b776229SDominik Haller clocks = <&clk IMX8MM_CLK_M4_DIV>; 51*7b776229SDominik Haller mboxes = <&mu 0 1 52*7b776229SDominik Haller &mu 1 1 53*7b776229SDominik Haller &mu 3 1>; 54*7b776229SDominik Haller mbox-names = "tx", "rx", "rxdb"; 55*7b776229SDominik Haller memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; 56*7b776229SDominik Haller syscon = <&src>; 57*7b776229SDominik Haller }; 58*7b776229SDominik Haller}; 59