/linux/drivers/clk/ingenic/ |
H A D | cgu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 5 * Copyright (c) 2013-2015 Imagination Technologies 13 #include <linux/clk-provider.h> 18 * struct ingenic_cgu_pll_info - information about a PLL 27 * @n_shift: the number of bits to shift the divider value by (ie. the 28 * index of the lowest bit of the divider value in the PLL's 30 * @n_bits: the size of the divider field in bits 31 * @n_offset: the divider value which encodes to 0 in the PLL's control 33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 34 * the index of the lowest bit of the post-VCO divider value in [all …]
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/linux/drivers/clk/bcm/ |
H A D | clk-kona.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 16 #include <linux/clk-provider.h> 24 #define BAD_CLK_NAME ((const char *)-1) 33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag)) 34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) 35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) 36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) 40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0) 44 #define policy_exists(policy) ((policy)->offset != 0) 55 #define hyst_exists(hyst) ((hyst)->offset != 0) [all …]
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H A D | clk-kona-setup.c | 1 // SPDX-License-Identifier: GPL-2.0-only 10 #include "clk-kona.h" 13 #define selector_clear_exists(sel) ((sel)->width = 0) 20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid() 23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid() 26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid() 29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid() 32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid() 35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid() 45 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger() [all …]
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/linux/drivers/clk/baikal-t1/ |
H A D | ccu-div.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * Baikal-T1 CCU Dividers interface driver 10 #include <linux/clk-provider.h> 17 * CCU Divider private clock IDs 21 #define CCU_SYS_SATA_CLK -1 22 #define CCU_SYS_XGMAC_CLK -2 25 * CCU Divider private flags 26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as 28 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1. 30 * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3]. [all …]
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H A D | ccu-div.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 * Baikal-T1 CCU Dividers interface driver 12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt 19 #include <linux/clk-provider.h> 27 #include "ccu-div.h" 35 GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD) 48 * getter available with non-constant mask support. 78 unsigned long divider) in ccu_div_var_update_clkdiv() argument 85 nd = ccu_div_lock_delay_ns(parent_rate, divider); in ccu_div_var_update_clkdiv() 87 if (div->features & CCU_DIV_LOCK_SHIFTED) in ccu_div_var_update_clkdiv() [all …]
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/linux/drivers/clk/ti/ |
H A D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * TI Divider Clock 7 * Tero Kristo <t-kristo@ti.com> 10 #include <linux/clk-provider.h> 26 for (clkt = table; clkt->div; clkt++) in _get_table_div() 27 if (clkt->val == val) in _get_table_div() 28 return clkt->div; in _get_table_div() 32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument 38 if (divider->table) { in _setup_mask() 41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask() [all …]
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/linux/drivers/media/i2c/cx25840/ |
H A D | cx25840-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 13 #include <media/drv-intf/cx25840.h> 14 #include <media/rc-core.h> 16 #include "cx25840-core.h" 117 return state ? state->ir_state : NULL; in to_ir_state() 122 * Rx and Tx Clock Divider register computations 124 * Note the largest clock divider value of 0xffff corresponds to: 135 d--; in count_to_clock_divider() 145 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument 147 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq() [all …]
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/linux/drivers/media/pci/cx23885/ |
H A D | cx23888-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 11 #include "cx23888-ir.h" 16 #include <media/v4l2-device.h> 17 #include <media/rc-core.h> 161 * Rx and Tx Clock Divider register computations 163 * Note the largest clock divider value of 0xffff corresponds to: 174 d--; in count_to_clock_divider() 184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument 186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq() 189 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument [all …]
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap44xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-output-names = "extalt_clkin_ck"; 12 clock-frequency = <59000000>; 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 clock-output-names = "pad_clks_src_ck"; 19 clock-frequency = <12000000>; 23 #clock-cells = <0>; [all …]
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H A D | omap54xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-output-names = "pad_clks_src_ck"; 12 clock-frequency = <12000000>; 16 #clock-cells = <0>; 17 compatible = "ti,gate-clock"; 18 clock-output-names = "pad_clks_ck"; 20 ti,bit-shift = <8>; 25 #clock-cells = <0>; [all …]
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/linux/drivers/clk/samsung/ |
H A D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only 12 * blocks which includes mux and divider blocks. There are a number of other 37 #include <linux/clk-provider.h> 40 #include "clk-cpu.h" 48 * struct exynos_cpuclk_regs - Register offsets for CPU related clocks 51 * @div_cpu0: offset of CPU DIV0 register (for modifying divider values) 52 * @div_cpu1: offset of CPU DIV1 register (for modifying divider values) 71 * struct exynos_cpuclk_chip - Chip specific data for CPU clock 83 * struct exynos_cpuclk - information about clock supplied to a CPU core 94 * @chip: chip-specific data for the CPU clock [all …]
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/linux/drivers/clk/zynqmp/ |
H A D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Zynq UltraScale+ MPSoC Divider support 5 * Copyright (C) 2016-2019 Xilinx 7 * Adjustable divider clock implementation 11 #include <linux/clk-provider.h> 13 #include "clk-zynqmp.h" 16 * DOC: basic adjustable divider clock that cannot gate 19 * prepare - clk_prepare only ensures that parents are prepared 20 * enable - clk_enable only ensures that parents are enabled 21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) [all …]
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/linux/drivers/clk/imx/ |
H A D | clk-divider-gate.c | 1 // SPDX-License-Identifier: GPL-2.0+ 7 #include <linux/clk-provider.h> 15 struct clk_divider divider; member 23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate() 32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro() 33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro() 37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro() 38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro() 49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate() 52 val = div_gate->cached_val; in clk_divider_gate_recalc_rate() [all …]
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_pll.c | 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 33 * amdgpu_pll_reduce_ratio - fractional number reduction 70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation 75 * @post_div: post divider 76 * @fb_div_max: feedback divider maximum 77 * @ref_div_max: reference divider maximum 78 * @fb_div: resulting feedback divider 79 * @ref_div: resulting reference divider 81 * Calculate feedback and reference divider for a given post divider. Makes 90 /* limit reference * post divider to a maximum */ in amdgpu_pll_get_fb_ref_div() [all …]
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/linux/Documentation/hwmon/ |
H A D | pc87360.rst | 12 Datasheets: No longer available 22 ----------------- 27 - 0: None 28 - **1**: Forcibly enable internal voltage and temperature channels, 30 - 2: Forcibly enable all voltage and temperature channels, except in9 31 - 3: Forcibly enable all voltage and temperature channels, including in9 33 Note that this parameter has no effect for the PC87360, PC87363 and PC87364 42 ----------- 56 PC87360 - 2 2 - 0xE1 57 PC87363 - 2 2 - 0xE8 [all …]
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H A D | adm9240.rst | 10 Addresses scanned: I2C 0x2c - 0x2f 20 Addresses scanned: I2C 0x2c - 0x2f 24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf 30 Addresses scanned: I2C 0x2c - 0x2f 37 - Frodo Looijaard <frodol@dds.nl>, 38 - Philip Edelbrock <phil@netroedge.com>, 39 - Michiel Rook <michiel@grendelproject.nl>, 40 - Grant Coady <gcoady.lk@gmail.com> with guidance 44 --------- 46 chip MSB 5-bit address. Each chip reports a unique manufacturer [all …]
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/linux/drivers/clk/ |
H A D | clk-aspeed.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 8 #include <linux/clk-provider.h> 10 #include <linux/reset-controller.h> 17 * struct aspeed_gate_data - Aspeed gated clocks 19 * @reset_idx: bit used to reset this IP in the reset register. -1 if no 34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure 35 * @hw: handle between common and hardware-specific interfaces 38 * @reset_idx: bit used to reset this IP in the reset register. -1 if no 40 * @flags: hardware-specific flags 59 * struct aspeed_reset - Aspeed reset controller [all …]
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H A D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> 7 * Adjustable divider clock implementation 10 #include <linux/clk-provider.h> 20 * DOC: basic adjustable divider clock that cannot gate 23 * prepare - clk_prepare only ensures that parents are prepared 24 * enable - clk_enable only ensures that parents are enabled 25 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) 26 * parent - fixed parent. No clk_set_parent support 29 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument [all …]
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/linux/drivers/gpu/drm/amd/display/dc/basics/ |
H A D | conversion.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 29 #define DIVIDER 10000 macro 31 /* S2D13 value in [-3.00...0.9999] */ 32 #define S2D13_MIN (-3 * DIVIDER) 33 #define S2D13_MAX (3 * DIVIDER) 49 if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor)) in fixed_point_to_int_frac() 77 * convert_float_matrix - This converts a double into HW register spec defined format S2D13. 85 dc_fixpt_from_fraction(S2D13_MIN, DIVIDER); in convert_float_matrix() 87 dc_fixpt_from_fraction(S2D13_MAX, DIVIDER); in convert_float_matrix() [all …]
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/linux/sound/soc/ti/ |
H A D | omap-dmic.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * omap-dmic.c -- OMAP ASoC DMIC DAI driver 5 * Copyright (C) 2010 - 2011 Texas Instruments 30 #include "omap-dmic.h" 31 #include "sdma-pcm.h" 53 writel_relaxed(val, dmic->io_base + reg); in omap_dmic_write() 58 return readl_relaxed(dmic->io_base + reg); in omap_dmic_read() 69 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled); in omap_dmic_start() 96 mutex_lock(&dmic->mutex); in omap_dmic_dai_startup() 99 dmic->active = 1; in omap_dmic_dai_startup() [all …]
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/linux/arch/powerpc/platforms/512x/ |
H A D | clock-commonclk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 12 #include <linux/clk-provider.h> 21 #include <dt-bindings/clock/mpc512x-clock.h> 85 * MPC5125 has many more differences: no MBX, no AXE, no VIU, no SPDIF, 86 * no PATA, no SATA, no PCI, two FECs (of different compatibility name), 89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet 292 val &= (1 << len) - 1; in get_bit_field() 305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult() 326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2() 350 cpmf = get_bit_field(&clkregs->spmr, 16, 4); in get_cpmf_mult_x2() [all …]
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/linux/sound/soc/codecs/ |
H A D | pcm512x.c | 1 // SPDX-License-Identifier: GPL-2.0-only 19 #include <sound/soc-dapm.h> 56 * there's no way I can see to get from a callback to the caller 66 regcache_mark_dirty(pcm512x->regmap); \ 67 regcache_cache_only(pcm512x->regmap, true); \ 230 ucontrol->value.integer.value[0] = pcm512x->overclock_pll; in pcm512x_overclock_pll_get() 245 return -EBUSY; in pcm512x_overclock_pll_put() 248 pcm512x->overclock_pll = ucontrol->value.integer.value[0]; in pcm512x_overclock_pll_put() 258 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp; in pcm512x_overclock_dsp_get() 273 return -EBUSY; in pcm512x_overclock_dsp_put() [all …]
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx53-usbarmory.dts | 8 * This file is dual-licensed: you can use it either under the terms 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 47 /dts-v1/; 52 compatible = "inversepath,imx53-usbarmory", "fsl,imx53"; 57 stdout-path = &uart1; 66 compatible = "gpio-leds"; 67 pinctrl-names = "default"; 68 pinctrl-0 = <&pinctrl_led>; 70 led-user { 73 linux,default-trigger = "heartbeat"; [all …]
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/linux/Documentation/devicetree/bindings/timer/ |
H A D | nxp,sysctr-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bai Ping <ping.bai@nxp.com> 22 - nxp,imx95-sysctr-timer 23 - nxp,sysctr-timer 34 clock-names: 37 nxp,no-divider: 38 description: if present, means there is no internal base clk divider. [all …]
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/linux/drivers/clk/berlin/ |
H A D | berlin2-avpll.c | 1 // SPDX-License-Identifier: GPL-2.0 6 * Alexandre Belloni <alexandre.belloni@free-electrons.com> 8 #include <linux/clk-provider.h> 15 #include "berlin2-avpll.h" 19 * VCO with 8 channels each, channel 8 is the odd-one-out and does 118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled() 119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled() 130 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable() 131 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_enable() 135 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable() [all …]
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