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Searched +full:mt8192 +full:- +full:infracfg (Results 1 – 15 of 15) sorted by relevance

/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
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H A Dmt8365.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/memory/mediatek,mt8365-larb-port.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mediatek,mt8365-power.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/linux/Documentation/devicetree/bindings/sound/
H A Dmt8192-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek AFE PCM controller for mt8192
10 - Jiaxin Yu <jiaxin.yu@mediatek.com>
11 - Shane Chien <shane.chien@mediatek.com>
15 const: mediatek,mt8192-audio
23 reset-names:
26 memory-region:
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/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8192-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek System Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 like reset and bus protection on MT8192.
19 - enum:
20 - mediatek,mt8192-topckgen
21 - mediatek,mt8192-infracfg
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/linux/drivers/clk/mediatek/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg…
6 obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o
7 obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o
8 obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o
9 obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o
10 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
133 by apmixedsys, topckgen, infracfg and pericfg on the
397 to PCI-E and USB.
427 to PCI-E and USB.
819 tristate "Clock driver for MediaTek MT8192"
825 This driver supports MediaTek MT8192 basic clocks.
828 tristate "Clock driver for MediaTek MT8192 audsys"
832 This driver supports MediaTek MT8192 audsys clocks.
835 tristate "Clock driver for MediaTek MT8192 camsys"
839 This driver supports MediaTek MT8192 camsys and camsys_raw clocks.
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H A Dclk-mt8192.c1 // SPDX-License-Identifier: GPL-2.0-only
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 #include "clk-gate.h"
14 #include "clk-mtk.h"
15 #include "clk-mux.h"
17 #include <dt-bindings/clock/mt8192-clk.h>
18 #include <dt-bindings/reset/mt8192-resets.h>
543 * spm_sel is the clock of the always-on co-processor.
583 mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1),
974 return -ENOMEM; in clk_mt8192_reg_mfg_mux_notifier()
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/linux/drivers/soc/mediatek/
H A Dmtk-infracfg.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/soc/mediatek/infracfg.h>
17 * mtk_infracfg_set_bus_protection - enable bus protection
18 * @infracfg: The infracfg regmap
28 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
35 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
38 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
40 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
48 * mtk_infracfg_clear_bus_protection - disable bus protection
49 * @infracfg: The infracfg regmap
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/linux/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <jianjun.wang@mediatek.com>
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
28 +-+-+-+-+-+-+-+-+
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/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mt8192-afe-common.h -- Mediatek 8192 audio driver definitions
16 #include "../common/mtk-base-afe.h"
17 #include "mt8192-reg.h"
109 /* SA suggest apply -0.3db to audio/speech path */
134 struct regmap *infracfg; member
H A Dmt8192-afe-clk.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt8192-afe-clk.c -- Mediatek 8192 afe clock ctrl
9 #include <linux/arm-smccc.h>
14 #include "mt8192-afe-clk.h"
15 #include "mt8192-afe-common.h"
66 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_set_audio_int_bus_parent()
69 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8192_set_audio_int_bus_parent()
70 afe_priv->clk[clk_id]); in mt8192_set_audio_int_bus_parent()
72 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8192_set_audio_int_bus_parent()
82 struct mt8192_afe_private *afe_priv = afe->platform_priv; in apll1_mux_setting()
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H A Dmt8192-afe-pcm.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
20 #include "../common/mtk-afe-fe-dai.h"
21 #include "../common/mtk-afe-platform-driver.h"
23 #include "mt8192-afe-common.h"
24 #include "mt8192-afe-clk.h"
25 #include "mt8192-afe-gpio.h"
26 #include "mt8192-interconnection.h"
50 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; in mt8192_memif_fs()
52 return mt8192_rate_transform(afe->dev, rate, id); in mt8192_memif_fs()
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/linux/Documentation/devicetree/bindings/soc/mediatek/
H A Dmtk-svs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Roger Lu <roger.lu@mediatek.com>
11 - Matthias Brugger <matthias.bgg@gmail.com>
12 - Kevin Hilman <khilman@kernel.org>
24 - mediatek,mt8183-svs
25 - mediatek,mt8186-svs
26 - mediatek,mt8188-svs
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/linux/drivers/pmdomain/mediatek/
H A Dmt6893-pm-domains.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/soc/mediatek/infracfg.h>
11 #include <dt-bindings/power/mediatek,mt6893-power.h>
12 #include "mtk-pm-domains.h"
75 * The register layout for this IP is very similar to MT8192 so where possible
/linux/drivers/iommu/
H A Dmtk_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
6 #include <linux/arm-smccc.h>
17 #include <linux/io-pgtable.h>
30 #include <linux/soc/mediatek/infracfg.h>
36 #include <dt-bindings/memory/mtk-memory-port.h>
152 ((((pdata)->flags) & (mask)) == (_x))
208 * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the
210 * 0x40000000-0x44000000.
272 * In the sharing pgtable case, list data->list to the global list like m4ulist.
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