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Searched +full:mt8186 +full:- +full:memory +full:- +full:port (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
22 register which control the iommu port is at each larb's register base. But
31 - enum:
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186-corsola.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
6 #include "mt8186.dtsi"
7 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/regulator/mediatek,mt6397-regulator.h>
26 stdout-path = "serial0:115200n8";
29 memory@40000000 {
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H A Dmt8365.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/memory/mediatek,mt8365-larb-port.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mediatek,mt8365-power.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_drm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
49 if (info->num_planes != 1) in mtk_drm_mode_fb_create()
50 return ERR_PTR(-EINVAL); in mtk_drm_mode_fb_create()
325 .min_width = 2, /* 2-pixel align when ethdr is bypassed */
334 { .compatible = "mediatek,mt2701-mmsys",
336 { .compatible = "mediatek,mt7623-mmsys",
338 { .compatible = "mediatek,mt2712-mmsys",
340 { .compatible = "mediatek,mt8167-mmsys",
342 { .compatible = "mediatek,mt8173-mmsys",
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/linux/drivers/memory/
H A Dmtk-smi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
6 #include <linux/arm-smccc.h>
20 #include <dt-bindings/memory/mt2701-larb-port.h>
21 #include <dt-bindings/memory/mtk-memory-port.h>
58 /* every register control 8 port, register offset 0x4 */
64 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
65 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
66 * or non-security.
155 struct device *smi_common_dev; /* common or sub-common dev */
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/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-afe-pcm.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
18 #include "../common/mtk-afe-platform-driver.h"
19 #include "../common/mtk-afe-fe-dai.h"
21 #include "mt8186-afe-common.h"
22 #include "mt8186-afe-clk.h"
23 #include "mt8186-afe-gpio.h"
24 #include "mt8186-interconnection.h"
46 struct snd_pcm_runtime *runtime = substream->runtime; in mt8186_fe_startup()
47 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; in mt8186_fe_startup()
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/linux/drivers/iommu/
H A Dmtk_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
6 #include <linux/arm-smccc.h>
17 #include <linux/io-pgtable.h>
36 #include <dt-bindings/memory/mtk-memory-port.h>
113 /* Macro for 5 bits length port ID field (default) */
116 /* Macro for 6 bits length port ID field */
152 ((((pdata)->flags) & (mask)) == (_x))
208 * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the
210 * 0x40000000-0x44000000.
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