Searched +full:mt8173 +full:- +full:mtu3 (Results 1 – 8 of 8) sorted by relevance
/linux/Documentation/devicetree/bindings/usb/ |
H A D | mediatek,mtu3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 14 - $ref: usb-drd.yaml 23 - enum: 24 - mediatek,mt2712-mtu3 25 - mediatek,mt8173-mtu3 26 - mediatek,mt8183-mtu3 [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | mediatek,tphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: MediaTek T-PHY Controller 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 14 The T-PHY controller supports physical layer functionality for a number of 17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and 18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode: 19 ----------------------------------- 67 pattern: "^t-phy(@[0-9a-f]+)?$" [all …]
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/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt8173.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <dt-bindings/clock/mt8173-clk.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/memory/mt8173-larb-port.h> 11 #include <dt-bindings/phy/phy.h> 12 #include <dt-bindings/power/mt8173-power.h> 13 #include <dt-bindings/reset/mt8173-resets.h> 14 #include <dt-bindings/gce/mt8173-gce.h> 15 #include <dt-bindings/thermal/thermal.h> [all …]
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H A D | mt8186.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 6 /dts-v1/; 7 #include <dt-bindings/clock/mt8186-clk.h> 8 #include <dt-bindings/gce/mt8186-gce.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/memory/mt8186-memory-port.h> 12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h> 13 #include <dt-bindings/power/mt8186-power.h> [all …]
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H A D | mt8195.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 /dts-v1/; 8 #include <dt-bindings/clock/mt8195-clk.h> 9 #include <dt-bindings/gce/mt8195-gce.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/memory/mt8195-memory-port.h> 13 #include <dt-bindings/phy/phy.h> 14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15 #include <dt-bindings/power/mt8195-power.h> [all …]
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H A D | mt8183.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 #include <dt-bindings/clock/mt8183-clk.h> 9 #include <dt-bindings/gce/mt8183-gce.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/memory/mt8183-larb-port.h> 13 #include <dt-bindings/power/mt8183-power.h> 14 #include <dt-bindings/reset/mt8183-resets.h> 15 #include <dt-bindings/phy/phy.h> 16 #include <dt-bindings/thermal/thermal.h> [all …]
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/linux/drivers/usb/mtu3/ |
H A D | mtu3_plat.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <linux/dma-mapping.h> 18 #include "mtu3.h" 22 /* u2-port0 should be powered on and enabled; */ 25 void __iomem *ibase = ssusb->ippc_base; in ssusb_check_clocks() 35 dev_err(ssusb->dev, "clks of sts1 are not stable!\n"); in ssusb_check_clocks() 42 dev_err(ssusb->dev, "mac2 clock is not stable\n"); in ssusb_check_clocks() 55 if (!ssusb->is_host) in wait_for_ip_sleep() 62 ret = readl_poll_timeout(ssusb->ippc_base + U3D_SSUSB_IP_PW_STS1, value, in wait_for_ip_sleep() 65 dev_err(ssusb->dev, "ip sleep failed!!!\n"); in wait_for_ip_sleep() [all …]
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H A D | mtu3_host.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * mtu3_dr.c - dual role switch and host glue layer 18 #include "mtu3.h" 21 /* mt8173 etc */ 65 * ip-sleep wakeup mode: 72 switch (ssusb->uwk_vers) { in ssusb_wakeup_ip_sleep_set() 74 reg = ssusb->uwk_reg_base + PERI_WK_CTRL1; in ssusb_wakeup_ip_sleep_set() 79 reg = ssusb->uwk_reg_base + PERI_WK_CTRL0; in ssusb_wakeup_ip_sleep_set() 84 reg = ssusb->uwk_reg_base + PERI_WK_CTRL0; in ssusb_wakeup_ip_sleep_set() 89 reg = ssusb->uwk_reg_base + PERI_WK_CTRL1_8195; in ssusb_wakeup_ip_sleep_set() [all …]
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