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Searched +full:mt8173 +full:- +full:hdmi (Results 1 – 16 of 16) sorted by relevance

/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,hdmi-ddc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI DDC
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
19 - mediatek,mt7623-hdmi-ddc
20 - mediatek,mt8167-hdmi-ddc
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H A Dmediatek,hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI Encoder
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
20 - mediatek,mt2701-hdmi
21 - mediatek,mt7623-hdmi
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H A Dmediatek,split.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
24 - enum:
25 - mediatek,mt8173-disp-split
26 - mediatek,mt8195-mdp3-split
27 - items:
28 - const: mediatek,mt6795-disp-split
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H A Dmediatek,cec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI CEC Controller
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The HDMI CEC controller handles hotplug detection and CEC communication.
19 - mediatek,mt7623-cec
20 - mediatek,mt8167-cec
21 - mediatek,mt8173-cec
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H A Dmediatek,dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
21 - enum:
22 - mediatek,mt2701-dpi
23 - mediatek,mt7623-dpi
24 - mediatek,mt8173-dpi
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/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,hdmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
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/linux/Documentation/devicetree/bindings/sound/
H A Dmt8173-rt5650.txt1 MT8173 with RT5650 CODECS and HDMI via I2S
4 - compatible : "mediatek,mt8173-rt5650"
5 - mediatek,audio-codec: the phandles of rt5650 codecs
6 and of the hdmi encoder node
7 - mediatek,platform: the phandle of MT8173 ASoC platform
10 - codec-capture : the subnode of rt5650 codec capture
11 Required codec-capture subnode properties:
12 - sound-dai: audio codec dai name on capture path
13 <&rt5650 0> : Default setting. Connect rt5650 I2S1 for capture. (dai_name = rt5645-aif1)
14 <&rt5650 1> : Connect rt5650 I2S2 for capture. (dai_name = rt5645-aif2)
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H A Dmt8173-rt5650-rt5676.txt1 MT8173 with RT5650 RT5676 CODECS and HDMI via I2S
4 - compatible : "mediatek,mt8173-rt5650-rt5676"
5 - mediatek,audio-codec: the phandles of rt5650 and rt5676 codecs
6 and of the hdmi encoder node
7 - mediatek,platform: the phandle of MT8173 ASoC platform
12 compatible = "mediatek,mt8173-rt5650-rt5676";
13 mediatek,audio-codec = <&rt5650 &rt5676 &hdmi0>;
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
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/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "phy-mtk-hdmi.h"
30 ret = clk_prepare_enable(hdmi_phy->pll); in mtk_hdmi_phy_power_on()
34 hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy); in mtk_hdmi_phy_power_on()
42 hdmi_phy->con in mtk_hdmi_phy_power_off()
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H A Dphy-mtk-hdmi-mt8173.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "phy-mtk-hdmi.h"
8 #include "phy-mtk-io.h"
90 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_prepare()
108 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_unprepare()
126 hdmi_phy->pll_rate = rate; in mtk_hdmi_pll_round_rate()
139 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_set_rate()
146 dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, in mtk_hdmi_pll_set_rate()
182 hdmi_ibias = hdmi_phy->ibias; in mtk_hdmi_pll_set_rate()
187 hdmi_ibias = hdmi_phy->ibias_up; in mtk_hdmi_pll_set_rate()
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/linux/sound/soc/mediatek/mt8173/
H A Dmt8173-afe-pcm.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/dma-mapping.h>
19 #include "mt8173-afe-common.h"
20 #include "../common/mtk-base-afe.h"
21 #include "../common/mtk-afe-platform-driver.h"
22 #include "../common/mtk-afe-fe-dai.h"
115 #define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24)
193 return -EINVAL; in mt8173_afe_i2s_fs()
202 return -EINVAL; in mt8173_afe_set_i2s()
205 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1); in mt8173_afe_set_i2s()
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/arm-smccc.h>
10 #include <linux/hdmi.h>
24 #include <sound/hdmi-codec.h>
190 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) in mtk_hdmi_read() argument
192 return readl(hdmi->regs + offset); in mtk_hdmi_read()
195 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) in mtk_hdmi_write() argument
197 writel(val, hdmi->regs + offset); in mtk_hdmi_write()
200 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) in mtk_hdmi_clear_bits() argument
202 void __iomem *reg = hdmi->regs + offset; in mtk_hdmi_clear_bits()
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H A Dmtk_hdmi_ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
68 writel(readl(ddc->regs + offset) | val, ddc->regs + offset); in sif_set_bit()
74 writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset); in sif_clr_bit()
80 return (readl(ddc->regs + offset) & val) == val; in sif_bit_is_set()
89 tmp = readl(ddc->regs + offset); in sif_write_mask()
92 writel(tmp, ddc->regs + offset); in sif_write_mask()
99 return (readl(ddc->regs + offset) & mask) >> shift; in sif_read_mask()
109 readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val, in ddcm_trigger_mode()
115 struct device *dev = ddc->adap.dev.parent; in mtk_hdmi_ddc_read_msg()
122 sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01); in mtk_hdmi_ddc_read_msg()
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H A Dmtk_cec.c1 // SPDX-License-Identifier: GPL-2.0-only
65 void __iomem *reg = cec->regs + offset; in mtk_cec_clear_bits()
76 void __iomem *reg = cec->regs + offset; in mtk_cec_set_bits()
87 u32 tmp = readl(cec->regs + offset) & ~mask; in mtk_cec_mask()
90 writel(tmp, cec->regs + offset); in mtk_cec_mask()
100 spin_lock_irqsave(&cec->lock, flags); in mtk_cec_set_hpd_event()
101 cec->hdmi_dev = hdmi_dev; in mtk_cec_set_hpd_event()
102 cec->hpd_event = hpd_event; in mtk_cec_set_hpd_event()
103 spin_unlock_irqrestore(&cec->lock, flags); in mtk_cec_set_hpd_event()
111 status = readl(cec->regs + RX_EVENT); in mtk_cec_hpd_high()
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