Searched +full:mt7621 +full:- +full:sysc (Results 1 – 11 of 11) sorted by relevance
/linux/Documentation/devicetree/bindings/clock/ |
H A D | mediatek,mt7621-sysc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MT7621 Clock 10 - Sergio Paracuellos <sergio.paracuellos@gmail.com> 13 The MT7621 has a PLL controller from where the cpu clock is provided 21 [1]: <include/dt-bindings/clock/mt7621-clk.h>. 28 [2]: <include/dt-bindings/reset/mt7621-reset.h>. 33 - const: mediatek,mt7621-sysc [all …]
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/linux/drivers/clk/ralink/ |
H A D | clk-mt7621.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Mediatek MT7621 Clock Driver 9 #include <linux/clk-provider.h> 14 #include <linux/reset-controller.h> 16 #include <dt-bindings/clock/mt7621-clk.h> 17 #include <dt-bindings/reset/mt7621-reset.h> 36 struct regmap *sysc; member 101 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_enable() local 103 return regmap_update_bits(sysc, SYSC_REG_CLKCFG1, in mt7621_gate_enable() 104 clk_gate->bit_idx, clk_gate->bit_idx); in mt7621_gate_enable() [all …]
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/linux/Documentation/devicetree/bindings/i2c/ |
H A D | mediatek,mt7621-i2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/i2c/mediatek,mt7621-i2c.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 - Stefan Roese <sr@denx.de> 10 title: Mediatek MT7621/MT7628 I2C master controller 13 - $ref: /schemas/i2c/i2c-controller.yaml# 17 const: mediatek,mt7621-i2c 25 clock-names: 31 reset-names: [all …]
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/linux/Documentation/devicetree/bindings/spi/ |
H A D | ralink,mt7621-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/ralink,mt7621-spi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 - Sergio Paracuellos <sergio.paracuellos@gmail.com> 10 title: Mediatek MT7621/MT7628 SPI controller 13 - $ref: /schemas/spi/spi-controller.yaml# 17 const: ralink,mt7621-spi 25 clock-names: 31 reset-names: [all …]
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/linux/Documentation/devicetree/bindings/watchdog/ |
H A D | mediatek,mt7621-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/watchdog/mediatek,mt7621-wdt.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sergio Paracuellos <sergio.paracuellos@gmail.com> 13 - $ref: watchdog.yaml# 17 const: mediatek,mt7621-wdt 25 phandle to system controller 'sysc' syscon node which 29 - compatible 30 - reg [all …]
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/linux/drivers/watchdog/ |
H A D | mt7621_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Ralink MT7621/MT7628 built-in hardware watchdog timer 37 struct regmap *sysc; member 61 rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART); in mt7621_wdt_ping() 70 w->timeout = t; in mt7621_wdt_set_timeout() 71 rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000); in mt7621_wdt_set_timeout() 83 rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT); in mt7621_wdt_start() 85 mt7621_wdt_set_timeout(w, w->timeout); in mt7621_wdt_start() 87 t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL); in mt7621_wdt_start() 89 rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t); in mt7621_wdt_start() [all …]
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/linux/arch/mips/ralink/ |
H A D | of.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> 24 #include <asm/mach-ralink/ralink_regs.h> 33 { .compatible = "mediatek,mt7621-memc" }, 34 { .compatible = "ralink,mt7620a-memc" }, 35 { .compatible = "ralink,rt2880-memc" }, 36 { .compatible = "ralink,rt3050-memc" }, 37 { .compatible = "ralink,rt3883-memc" }, 42 { .compatible = "mediatek,mt7621-sysc" }, 43 { .compatible = "ralink,mt7620-sysc" }, [all …]
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/linux/Documentation/devicetree/bindings/net/dsa/ |
H A D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Arınç ÜNAL <arinc.unal@arinc9.com> 11 - Landen Chao <Landen.Chao@mediatek.com> 12 - DENG Qingfang <dqfext@gmail.com> 13 - Sean Wang <sean.wang@mediatek.com> 14 - Daniel Golle <daniel@makrotopia.org> 17 There are three versions of MT7530, standalone, in a multi-chip module and 18 built-into a SoC. [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | mediatek,mt7621-pci-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Mediatek Mt7621 PCIe PHY 10 - Sergio Paracuellos <sergio.paracuellos@gmail.com> 14 const: mediatek,mt7621-pci-phy 22 "#phy-cells": 24 description: selects if the phy is dual-ported 27 - compatible [all …]
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/linux/arch/mips/boot/dts/ralink/ |
H A D | mt7628a.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 #address-cells = <1>; 5 #size-cells = <1>; 6 compatible = "ralink,mt7628a-soc"; 9 #address-cells = <1>; 10 #size-cells = <0>; 19 resetc: reset-controller { 20 compatible = "ralink,rt2880-reset"; 21 #reset-cells = <1>; 24 cpuintc: interrupt-controller { [all …]
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/linux/ |
H A D | MAINTAINERS | 5 --------------------------------------------------- 21 W: *Web-page* with status/info 23 B: URI for where to file *bugs*. A web-page with detailed bug 28 patches to the given subsystem. This is either an in-tree file, 29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst 46 N: [^a-z]tegra all files whose path contains tegra 64 ---------------- 83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS) 85 L: linux-scsi@vger.kernel.org 88 F: drivers/scsi/3w-* [all …]
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