Home
last modified time | relevance | path

Searched +full:mt2701 +full:- +full:ethsys (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,ethsys.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek ethsys controller
10 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
13 - James Liao <jamesjj.liao@mediatek.com>
18 - items:
19 - enum:
20 - mediatek,mt2701-ethsys
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
[all …]
/linux/drivers/clk/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 bool "Clock driver for MediaTek MT2701"
27 This driver supports MediaTek MT2701 basic clocks.
30 bool "Clock driver for MediaTek MT2701 mmsys"
33 This driver supports MediaTek MT2701 mmsys clocks.
36 bool "Clock driver for MediaTek MT2701 imgsys"
39 This driver supports MediaTek MT2701 imgsys clocks.
42 bool "Clock driver for MediaTek MT2701 vdecsys"
45 This driver supports MediaTek MT2701 vdecsys clocks.
48 bool "Clock driver for MediaTek MT2701 hifsys"
[all …]
H A Dclk-mt2701-eth.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
10 #include "clk-mtk.h"
11 #include "clk-gate.h"
13 #include <dt-bindings/clock/mt2701-clk.h>
49 { .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
58 .name = "clk-mt2701-eth",
64 MODULE_DESCRIPTION("MediaTek MT2701 Ethernet clocks driver");
/linux/Documentation/devicetree/bindings/net/
H A Dmediatek,net.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dmediatek,mt7622-hsdma.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/mediatek,mt7622-hsdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek High-Speed DMA Controller
10 - Sean Wang <sean.wang@mediatek.com>
13 - $ref: dma-controller.yaml#
18 - mediatek,mt7622-hsdma
19 - mediatek,mt7623-hsdma
30 clock-names:
[all …]
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
/linux/drivers/pmdomain/mediatek/
H A Dmtk-scpsys.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <dt-bindings/power/mt2701-power.h>
17 #include <dt-bindings/power/mt2712-power.h>
18 #include <dt-bindings/power/mt6797-power.h>
19 #include <dt-bindings/power/mt7622-power.h>
20 #include <dt-bindings/power/mt7623a-power.h>
21 #include <dt-bindings/power/mt8173-power.h>
28 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
38 #define SPM_BDP_PWR_CON 0x029c /* MT2701 */
112 * struct scp_domain_data - scp domain data for power on/off flow
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
35 static int mtk_msg_level = -1;
37 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
291 __raw_writel(val, eth->base + reg); in mtk_w32()
296 return __raw_readl(eth->base + reg); in mtk_r32()
322 dev_err(eth->dev, "mdio: MDIO timeout\n"); in mtk_mdio_busy_wait()
[all …]