| /linux/drivers/pci/controller/ |
| H A D | pcie-iproc-msi.c | 8 #include <linux/irqchip/irq-msi-lib.h>
10 #include <linux/msi.h>
35 /* Size of each MSI address region */
53 * struct iproc_msi_grp - iProc MSI group
55 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
58 * @msi: pointer to iProc MSI data
63 struct iproc_msi *msi; member
69 * struct iproc_msi - iProc event queue based MSI
71 * Only meant to be used on platforms without MSI support integrated into the
75 * @reg_offsets: MSI register offsets
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| H A D | pcie-altera-msi.c | 3 * Altera PCIe MSI support
12 #include <linux/irqchip/irq-msi-lib.h>
16 #include <linux/msi.h>
41 static inline void msi_writel(struct altera_msi *msi, const u32 value, in msi_writel() argument
44 writel_relaxed(value, msi->csr_base + reg); in msi_writel()
47 static inline u32 msi_readl(struct altera_msi *msi, const u32 reg) in msi_readl() argument
49 return readl_relaxed(msi->csr_base + reg); in msi_readl()
55 struct altera_msi *msi; in altera_msi_isr() local
61 msi = irq_desc_get_handler_data(desc); in altera_msi_isr()
63 while ((status = msi_readl(msi, MSI_STATUS)) != 0) { in altera_msi_isr()
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| H A D | pci-xgene-msi.c | 3 * APM X-Gene MSI Driver
14 #include <linux/msi.h>
16 #include <linux/irqchip/irq-msi-lib.h>
49 * X-Gene v1 has 16 frames of MSI termination registers MSInIRx, where n is
54 * Each register supports 16 MSI vectors (0..15) to generate interrupts. A
60 * Additionally, each MSI termination frame has 1 MSIINTn register (n is
61 * 0..15) to indicate the MSI pending status caused by any of its 8
66 * There is one GIC IRQ assigned for each MSI termination frame, 16 in
92 static u32 xgene_msi_ir_read(struct xgene_msi *msi, u32 msi_grp, u32 msir_idx) in xgene_msi_ir_read() argument
94 return readl_relaxed(msi->msi_regs + MSI_IR0 + in xgene_msi_ir_read()
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| H A D | pcie-xilinx-dma-pl.c | 10 #include <linux/irqchip/irq-msi-lib.h>
14 #include <linux/msi.h>
47 IMR(MSI) | \
77 /* Number of MSI IRQs */
112 * @msi: MSI information
127 struct xilinx_msi msi; member
272 struct xilinx_msi *msi; in xilinx_pl_dma_pcie_msi_handler_high() local
277 msi = &port->msi; in xilinx_pl_dma_pcie_msi_handler_high()
283 virq = irq_find_mapping(msi->dev_domain, bit); in xilinx_pl_dma_pcie_msi_handler_high()
295 struct xilinx_msi *msi; in xilinx_pl_dma_pcie_msi_handler_low() local
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| H A D | pcie-rcar-host.c | 20 #include <linux/irqchip/irq-msi-lib.h>
25 #include <linux/msi.h>
51 struct rcar_msi msi; member
95 static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi) in msi_to_host() argument
97 return container_of(msi, struct rcar_pcie_host, msi); in msi_to_host()
485 /* Enable MSI */ in rcar_pcie_hw_init()
573 struct rcar_msi *msi = &host->msi; in rcar_pcie_msi_irq() local
579 /* MSI & INTx share an interrupt - we only handle MSI here */ in rcar_pcie_msi_irq()
587 ret = generic_handle_domain_irq(msi->domain->parent, index); in rcar_pcie_msi_irq()
589 /* Unknown MSI, just clear it */ in rcar_pcie_msi_irq()
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| /linux/arch/powerpc/sysdev/ |
| H A D | fsl_msi.c | 11 #include <linux/msi.h>
39 #define msi_hwirq(msi, msir_index, intr_index) \ argument
40 ((msir_index) << (msi)->srs_shift | \
41 ((intr_index) << (msi)->ibs_shift))
63 * in the cascade interrupt. So, this MSI interrupt has been acked
78 seq_printf(p, "fsl-msi-%d", cascade_virq); in fsl_msi_print_chip()
152 /* If the msi-address-64 property exists, then use it */ in fsl_compose_msi_msg()
153 reg = of_get_property(hose->dn, "msi-address-64", &len); in fsl_compose_msi_msg()
164 * that neither MSI nor MSI-X can work fine. in fsl_compose_msi_msg()
165 * This is a workaround to allow MSI-X to function in fsl_compose_msi_msg()
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
17 they can address. An MSI controller may feature a number of doorbells.
22 MSI controllers may have restrictions on permitted payloads.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
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| H A D | fsl,mpic-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
14 Freescale MSI driver calculates the address of MSIIR (in the MSI register
15 block) and sets that address as the MSI message address.
39 this. The address specified in the msi-address-64 property is the PCI
50 - fsl,mpic-msi
51 - fsl,mpic-msi-v4.3
52 - fsl,ipic-msi
53 - fsl,vmpic-msi
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| H A D | fsl,ls-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
24 - fsl,ls1012a-msi
25 - fsl,ls1021a-msi
26 - fsl,ls1043a-msi
27 - fsl,ls1043a-v1.1-msi
28 - fsl,ls1046a-msi
33 '#msi-cells':
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| H A D | sophgo,sg2042-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml#
7 title: Sophgo SG2042 MSI Controller
14 PCIe MSI to PLIC interrupts.
17 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
22 - sophgo,sg2042-msi
23 - sophgo,sg2044-msi
28 - description: msi doorbell address
35 msi-controller: true
37 msi-ranges:
40 "#msi-cells":
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| H A D | loongson,pch-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
7 title: Loongson PCH MSI Controller
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
27 to PCH MSI.
32 loongson,msi-num-vecs:
35 to PCH MSI.
40 msi-controller: true
45 - msi-controller
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| H A D | msi-controller.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
7 title: MSI controller
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
18 "#msi-cells":
20 The number of cells in an msi-specifier, required if not zero.
26 The meaning of the msi-specifier is defined by the device tree
27 binding of the specific MSI controller.
30 msi-controller:
32 Identifies the node as an MSI controller.
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| H A D | al,alpine-msix.yaml | 21 msi-controller: true
23 al,msi-base-spi:
24 description: SPI base of the MSI frame
27 al,msi-num-spis:
28 description: number of SPIs assigned to the MSI frame, relative to SPI0
34 - msi-controller
35 - al,msi-base-spi
36 - al,msi-num-spis
42 msi-controller@fbe00000 {
46 msi-controller;
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| /linux/include/linux/ |
| H A D | msi.h | 6 * This header file contains MSI data structures and functions which are
9 * - PCI/MSI core code
10 * - MSI interrupt domain implementations
12 * dealing with low level MSI details.
15 * especially storing MSI descriptor pointers in random code is considered
26 #include <asm/msi.h>
52 * msi_msg - Representation of a MSI message
53 * @address_lo: Low 32 bits of msi message address
55 * @address_hi: High 32 bits of msi message address
58 * @data: MSI message data (usually 16 bits)
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| /linux/arch/arm64/kvm/vgic/ |
| H A D | vgic-irqfd.c | 55 e->msi.address_lo = ue->u.msi.address_lo; in kvm_set_routing_entry()
56 e->msi.address_hi = ue->u.msi.address_hi; in kvm_set_routing_entry()
57 e->msi.data = ue->u.msi.data; in kvm_set_routing_entry()
58 e->msi.flags = ue->flags; in kvm_set_routing_entry()
59 e->msi.devid = ue->u.msi.devid; in kvm_set_routing_entry()
70 struct kvm_msi *msi) in kvm_populate_msi() argument
72 msi->address_lo = e->msi.address_lo; in kvm_populate_msi()
73 msi->address_hi = e->msi.address_hi; in kvm_populate_msi()
74 msi->data = e->msi.data; in kvm_populate_msi()
75 msi->flags = e->msi.flags; in kvm_populate_msi()
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| /linux/drivers/pci/msi/ |
| H A D | api.c | 3 * PCI MSI/MSI-X — Exported APIs for device drivers
14 #include "msi.h"
17 * pci_enable_msi() - Enable MSI interrupt mode on device
20 * Legacy device driver API to enable MSI interrupts mode on device and
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
63 * pci_msix_vec_count() - Get number of MSI-X interrupt vectors on device
66 * Return: number of MSI-X interrupt vectors available on this device
67 * (i.e., the device's MSI-X capability structure "table size"), -EINVAL
68 * if the device is not MSI-X capable, other errnos otherwise.
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| H A D | irqdomain.c | 3 * PCI Message Signaled Interrupt (MSI) - irqdomain support
9 #include "msi.h"
36 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
37 * @irq_data: Pointer to interrupt data of the MSI interrupt
45 * For MSI-X desc->irq is always equal to irq_data->irq. For in pci_msi_domain_write_msg()
46 * MSI only the first interrupt of MULTI MSI passes the test. in pci_msi_domain_write_msg()
53 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
54 * @desc: Pointer to the MSI descriptor
104 * pci_msi_create_irq_domain - Create a MSI interrupt domain
106 * @info: MSI domain info
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| H A D | msi.c | 3 * PCI Message Signaled Interrupt (MSI)
16 #include "msi.h"
21 * pci_msi_supported - check whether MSI may be enabled on a device
22 * @dev: pointer to the pci_dev data structure of MSI device function
26 * to determine if MSI/-X are supported for the device. If MSI/-X is
33 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
49 * Any bridge which does NOT route MSI transactions from its in pci_msi_supported()
59 * the NO_MSI flag when no MSI domain is found for this bridge in pci_msi_supported()
79 * vs. msi_device_data_release() in the MSI core code.
97 * Ordering vs. devres: msi device data has to be installed first so that
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| /linux/arch/mips/pci/ |
| H A D | msi-octeon.c | 10 #include <linux/msi.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
43 * Number of MSI IRQs used. This variable is set up in
49 * arch_setup_msi_irq() - setup MSI IRQs for a device
50 * @dev: Device requesting MSI interrupts
51 * @desc: MSI descriptor
53 * Called when a driver requests MSI interrupts instead of the
55 * for MSI devices that support them. A device can override this by
56 * programming the MSI control bits [6:4] before calling
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| /linux/drivers/ntb/ |
| H A D | msi.c | 6 #include <linux/msi.h>
19 * ntb_msi_init() - Initialize the MSI context
23 * It initializes the context for MSI operations and maps
45 ntb->msi = devm_kzalloc(&ntb->dev, struct_size(ntb->msi, peer_mws, peers), in ntb_msi_init()
47 if (!ntb->msi) in ntb_msi_init()
50 ntb->msi->desc_changed = desc_changed; in ntb_msi_init()
60 ntb->msi->peer_mws[i] = devm_ioremap(&ntb->dev, mw_phys_addr, in ntb_msi_init()
62 if (!ntb->msi->peer_mws[i]) { in ntb_msi_init()
72 if (ntb->msi->peer_mws[i]) in ntb_msi_init()
73 devm_iounmap(&ntb->dev, ntb->msi->peer_mws[i]); in ntb_msi_init()
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| /linux/arch/riscv/kvm/ |
| H A D | vm.c | 72 struct kvm_msi msi; in kvm_set_msi() local
77 msi.address_lo = e->msi.address_lo; in kvm_set_msi()
78 msi.address_hi = e->msi.address_hi; in kvm_set_msi()
79 msi.data = e->msi.data; in kvm_set_msi()
80 msi.flags = e->msi.flags; in kvm_set_msi()
81 msi.devid = e->msi.devid; in kvm_set_msi()
83 return kvm_riscv_aia_inject_msi(kvm, &msi); in kvm_set_msi()
136 e->msi.address_lo = ue->u.msi.address_lo; in kvm_set_routing_entry()
137 e->msi.address_hi = ue->u.msi.address_hi; in kvm_set_routing_entry()
138 e->msi.data = ue->u.msi.data; in kvm_set_routing_entry()
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| /linux/drivers/pci/controller/mobiveil/ |
| H A D | pcie-mobiveil-host.c | 15 #include <linux/irqchip/irq-msi-lib.h>
20 #include <linux/msi.h>
89 struct mobiveil_msi *msi = &rp->msi; in mobiveil_pcie_isr() local
96 * The core provides a single interrupt for both INTx/MSI messages. in mobiveil_pcie_isr()
97 * So we'll read both INTx and MSI status in mobiveil_pcie_isr()
135 /* read extra MSI status register */ in mobiveil_pcie_isr()
138 /* handle MSI interrupts */ in mobiveil_pcie_isr()
144 * once we pop not only the MSI data but also address in mobiveil_pcie_isr()
145 * from MSI hardware FIFO. So keeping these following in mobiveil_pcie_isr()
152 dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n", in mobiveil_pcie_isr()
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| /linux/kernel/irq/ |
| H A D | msi.c | 14 #include <linux/msi.h>
26 * struct msi_device_data - MSI per device data
27 * @properties: MSI properties which are interesting to drivers
28 * @mutex: Mutex protecting the MSI descriptor store
29 * @__domains: Internal data for per device MSI domains
40 * struct msi_ctrl - MSI internal management control structure
45 * than the range due to PCI/multi-MSI.
105 struct msi_device_data *md = dev->msi.data; in msi_insert_desc()
141 * msi_domain_insert_msi_desc - Allocate and initialize a MSI descriptor and
146 * @init_desc: Pointer to an MSI descriptor to initialize the new descriptor
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | pci-ep.yaml | 24 - description: Device ID (see msi-map) base
56 msi-map:
58 Maps a Device ID to an MSI and associated MSI specifier data.
60 A PCI Endpoint (EP) can use MSI as a doorbell function. This is achieved by
61 mapping the MSI controller's address into PCI BAR<n>. The PCI Root Complex
82 (device-id-base, msi, msi-base,length).
85 associated with the listed MSI, with the MSI specifier
86 (id - id-base + msi-base).
92 - description: phandle to msi-controller node
93 - description: (optional) The msi-specifier produced for the first
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| /linux/drivers/irqchip/ |
| H A D | irq-msi-lib.c | 7 #include <linux/irqchip/irq-msi-lib.h>
10 * msi_lib_init_dev_msi_info - Domain info setup for MSI domains
18 * This function is to be used for all types of MSI domains above the root
39 * MSI parent domain specific settings. For now there is only the in msi_lib_init_dev_msi_info()
40 * root parent domain, e.g. NEXUS, acting as a MSI parent, but it is in msi_lib_init_dev_msi_info()
41 * possible to stack MSI parents. See x86 vector -> irq remapping in msi_lib_init_dev_msi_info()
63 * Per device MSI should never have any MSI feature bits in msi_lib_init_dev_msi_info()
71 /* Core managed MSI descriptors */ in msi_lib_init_dev_msi_info()
88 * Mask out the domain specific MSI feature flags which are not in msi_lib_init_dev_msi_info()
102 * The device MSI domain can never have a set affinity callback. It in msi_lib_init_dev_msi_info()
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