Home
last modified time | relevance | path

Searched full:msi (Results 1 – 25 of 779) sorted by relevance

12345678910>>...32

/linux/drivers/pci/controller/
H A Dpcie-iproc-msi.c8 #include <linux/irqchip/irq-msi-lib.h>
10 #include <linux/msi.h>
35 /* Size of each MSI address region */
53 * struct iproc_msi_grp - iProc MSI group
55 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
58 * @msi: pointer to iProc MSI data
63 struct iproc_msi *msi; member
69 * struct iproc_msi - iProc event queue based MSI
71 * Only meant to be used on platforms without MSI support integrated into the
75 * @reg_offsets: MSI register offsets
[all …]
H A Dpcie-altera-msi.c3 * Altera PCIe MSI support
12 #include <linux/irqchip/irq-msi-lib.h>
16 #include <linux/msi.h>
41 static inline void msi_writel(struct altera_msi *msi, const u32 value, in msi_writel() argument
44 writel_relaxed(value, msi->csr_base + reg); in msi_writel()
47 static inline u32 msi_readl(struct altera_msi *msi, const u32 reg) in msi_readl() argument
49 return readl_relaxed(msi->csr_base + reg); in msi_readl()
55 struct altera_msi *msi; in altera_msi_isr() local
61 msi = irq_desc_get_handler_data(desc); in altera_msi_isr()
63 while ((status = msi_readl(msi, MSI_STATUS)) != 0) { in altera_msi_isr()
[all …]
H A Dpci-xgene-msi.c3 * APM X-Gene MSI Driver
14 #include <linux/msi.h>
16 #include <linux/irqchip/irq-msi-lib.h>
49 * X-Gene v1 has 16 frames of MSI termination registers MSInIRx, where n is
54 * Each register supports 16 MSI vectors (0..15) to generate interrupts. A
60 * Additionally, each MSI termination frame has 1 MSIINTn register (n is
61 * 0..15) to indicate the MSI pending status caused by any of its 8
66 * There is one GIC IRQ assigned for each MSI termination frame, 16 in
92 static u32 xgene_msi_ir_read(struct xgene_msi *msi, u32 msi_grp, u32 msir_idx) in xgene_msi_ir_read() argument
94 return readl_relaxed(msi->msi_regs + MSI_IR0 + in xgene_msi_ir_read()
[all …]
H A Dpcie-xilinx-dma-pl.c10 #include <linux/irqchip/irq-msi-lib.h>
14 #include <linux/msi.h>
47 IMR(MSI) | \
77 /* Number of MSI IRQs */
112 * @msi: MSI information
127 struct xilinx_msi msi; member
272 struct xilinx_msi *msi; in xilinx_pl_dma_pcie_msi_handler_high() local
277 msi = &port->msi; in xilinx_pl_dma_pcie_msi_handler_high()
283 virq = irq_find_mapping(msi->dev_domain, bit); in xilinx_pl_dma_pcie_msi_handler_high()
295 struct xilinx_msi *msi; in xilinx_pl_dma_pcie_msi_handler_low() local
[all …]
H A Dpcie-rcar-host.c21 #include <linux/irqchip/irq-msi-lib.h>
26 #include <linux/msi.h>
52 struct rcar_msi msi; member
87 static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi) in msi_to_host() argument
89 return container_of(msi, struct rcar_pcie_host, msi); in msi_to_host()
476 /* Enable MSI */ in rcar_pcie_hw_init()
564 struct rcar_msi *msi = &host->msi; in rcar_pcie_msi_irq() local
570 /* MSI & INTx share an interrupt - we only handle MSI here */ in rcar_pcie_msi_irq()
578 ret = generic_handle_domain_irq(msi->domain, index); in rcar_pcie_msi_irq()
580 /* Unknown MSI, just clear it */ in rcar_pcie_msi_irq()
[all …]
H A Dpcie-brcmstb.c15 #include <linux/irqchip/irq-msi-lib.h>
22 #include <linux/msi.h>
211 /* MSI target addresses */
318 int nr; /* No. of MSI available, depends on chip */
332 struct brcm_msi *msi; member
551 struct brcm_msi *msi; in brcm_pcie_msi_isr() local
556 msi = irq_desc_get_handler_data(desc); in brcm_pcie_msi_isr()
557 dev = msi->dev; in brcm_pcie_msi_isr()
559 status = readl(msi->intr_base + MSI_INT_STATUS); in brcm_pcie_msi_isr()
560 status >>= msi->legacy_shift; in brcm_pcie_msi_isr()
[all …]
/linux/arch/powerpc/sysdev/
H A Dfsl_msi.c11 #include <linux/msi.h>
39 #define msi_hwirq(msi, msir_index, intr_index) \ argument
40 ((msir_index) << (msi)->srs_shift | \
41 ((intr_index) << (msi)->ibs_shift))
63 * in the cascade interrupt. So, this MSI interrupt has been acked
78 seq_printf(p, "fsl-msi-%d", cascade_virq); in fsl_msi_print_chip()
152 /* If the msi-address-64 property exists, then use it */ in fsl_compose_msi_msg()
153 reg = of_get_property(hose->dn, "msi-address-64", &len); in fsl_compose_msi_msg()
164 * that neither MSI nor MSI-X can work fine. in fsl_compose_msi_msg()
165 * This is a workaround to allow MSI-X to function in fsl_compose_msi_msg()
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
17 they can address. An MSI controller may feature a number of doorbells.
22 MSI controllers may have restrictions on permitted payloads.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
[all …]
H A Dfsl,mpic-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
14 Freescale MSI driver calculates the address of MSIIR (in the MSI register
15 block) and sets that address as the MSI message address.
39 this. The address specified in the msi-address-64 property is the PCI
50 - fsl,mpic-msi
51 - fsl,mpic-msi-v4.3
52 - fsl,ipic-msi
53 - fsl,vmpic-msi
[all …]
H A Dfsl,ls-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
24 - fsl,ls1012a-msi
25 - fsl,ls1021a-msi
26 - fsl,ls1043a-msi
27 - fsl,ls1043a-v1.1-msi
28 - fsl,ls1046a-msi
33 '#msi-cells':
[all …]
H A Dsophgo,sg2042-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml#
7 title: Sophgo SG2042 MSI Controller
14 PCIe MSI to PLIC interrupts.
17 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
22 - sophgo,sg2042-msi
23 - sophgo,sg2044-msi
28 - description: msi doorbell address
35 msi-controller: true
37 msi-ranges:
40 "#msi-cells":
[all …]
H A Dloongson,pch-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
7 title: Loongson PCH MSI Controller
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
27 to PCH MSI.
32 loongson,msi-num-vecs:
35 to PCH MSI.
40 msi-controller: true
45 - msi-controller
[all …]
H A Dmsi-controller.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
7 title: MSI controller
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
18 "#msi-cells":
20 The number of cells in an msi-specifier, required if not zero.
26 The meaning of the msi-specifier is defined by the device tree
27 binding of the specific MSI controller.
30 msi-controller:
32 Identifies the node as an MSI controller.
[all …]
H A Dal,alpine-msix.yaml21 msi-controller: true
23 al,msi-base-spi:
24 description: SPI base of the MSI frame
27 al,msi-num-spis:
28 description: number of SPIs assigned to the MSI frame, relative to SPI0
34 - msi-controller
35 - al,msi-base-spi
36 - al,msi-num-spis
42 msi-controller@fbe00000 {
46 msi-controller;
[all …]
H A Daltr,msi-controller.yaml5 $id: http://devicetree.org/schemas/interrupt-controller/altr,msi-controller.yaml#
8 title: Altera PCIe MSI controller
16 - altr,msi-1.0
31 msi-controller: true
44 - msi-controller
48 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
56 msi@ff200000 {
57 compatible = "altr,msi-1.0";
63 msi-controller;
H A Dapm,xgene1-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/apm,xgene1-msi.yaml#
7 title: AppliedMicro X-Gene v1 PCIe MSI controller
14 const: apm,xgene1-msi
16 msi-controller: true
26 - msi-controller
34 msi@79000000 {
35 compatible = "apm,xgene1-msi";
36 msi-controller;
/linux/drivers/ntb/
H A Dmsi.c6 #include <linux/msi.h>
19 * ntb_msi_init() - Initialize the MSI context
23 * It initializes the context for MSI operations and maps
45 ntb->msi = devm_kzalloc(&ntb->dev, struct_size(ntb->msi, peer_mws, peers), in ntb_msi_init()
47 if (!ntb->msi) in ntb_msi_init()
50 ntb->msi->desc_changed = desc_changed; in ntb_msi_init()
60 ntb->msi->peer_mws[i] = devm_ioremap(&ntb->dev, mw_phys_addr, in ntb_msi_init()
62 if (!ntb->msi->peer_mws[i]) { in ntb_msi_init()
72 if (ntb->msi->peer_mws[i]) in ntb_msi_init()
73 devm_iounmap(&ntb->dev, ntb->msi->peer_mws[i]); in ntb_msi_init()
[all …]
/linux/arch/mips/pci/
H A Dmsi-octeon.c10 #include <linux/msi.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
43 * Number of MSI IRQs used. This variable is set up in
49 * arch_setup_msi_irq() - setup MSI IRQs for a device
50 * @dev: Device requesting MSI interrupts
51 * @desc: MSI descriptor
53 * Called when a driver requests MSI interrupts instead of the
55 * for MSI devices that support them. A device can override this by
56 * programming the MSI control bits [6:4] before calling
[all …]
/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c15 #include <linux/irqchip/irq-msi-lib.h>
20 #include <linux/msi.h>
89 struct mobiveil_msi *msi = &rp->msi; in mobiveil_pcie_isr() local
96 * The core provides a single interrupt for both INTx/MSI messages. in mobiveil_pcie_isr()
97 * So we'll read both INTx and MSI status in mobiveil_pcie_isr()
135 /* read extra MSI status register */ in mobiveil_pcie_isr()
138 /* handle MSI interrupts */ in mobiveil_pcie_isr()
144 * once we pop not only the MSI data but also address in mobiveil_pcie_isr()
145 * from MSI hardware FIFO. So keeping these following in mobiveil_pcie_isr()
152 dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n", in mobiveil_pcie_isr()
[all …]
/linux/arch/riscv/kvm/
H A Dvm.c72 struct kvm_msi msi; in kvm_set_msi() local
77 msi.address_lo = e->msi.address_lo; in kvm_set_msi()
78 msi.address_hi = e->msi.address_hi; in kvm_set_msi()
79 msi.data = e->msi.data; in kvm_set_msi()
80 msi.flags = e->msi.flags; in kvm_set_msi()
81 msi.devid = e->msi.devid; in kvm_set_msi()
83 return kvm_riscv_aia_inject_msi(kvm, &msi); in kvm_set_msi()
136 e->msi.address_lo = ue->u.msi.address_lo; in kvm_set_routing_entry()
137 e->msi.address_hi = ue->u.msi.address_hi; in kvm_set_routing_entry()
138 e->msi.data = ue->u.msi.data; in kvm_set_routing_entry()
[all …]
/linux/drivers/pci/msi/
H A Dmsi.c3 * PCI Message Signaled Interrupt (MSI)
16 #include "msi.h"
21 * pci_msi_supported - check whether MSI may be enabled on a device
22 * @dev: pointer to the pci_dev data structure of MSI device function
26 * to determine if MSI/-X are supported for the device. If MSI/-X is
33 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
49 * Any bridge which does NOT route MSI transactions from its in pci_msi_supported()
59 * the NO_MSI flag when no MSI domain is found for this bridge in pci_msi_supported()
79 * vs. msi_device_data_release() in the MSI core code.
107 * Ordering vs. devres: msi device data has to be installed first so that
[all …]
/linux/drivers/virt/acrn/
H A Dvm.c97 * acrn_msi_inject() - Inject a MSI interrupt into a User VM
99 * @msi_addr: The MSI address
100 * @msi_data: The MSI data
106 struct acrn_msi_entry *msi; in acrn_msi_inject() local
110 msi = kzalloc_obj(*msi, GFP_ATOMIC); in acrn_msi_inject()
111 if (!msi) in acrn_msi_inject()
118 msi->msi_addr = msi_addr; in acrn_msi_inject()
119 msi->msi_data = msi_data; in acrn_msi_inject()
120 ret = hcall_inject_msi(vm->vmid, virt_to_phys(msi)); in acrn_msi_inject()
123 "Failed to inject MSI to VM %u!\n", vm->vmid); in acrn_msi_inject()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
H A Dbase.c35 if (pci && pci->msi) in nvkm_pci_msi_rearm()
128 /* Ensure MSI interrupts are armed, for the case where there are in nvkm_pci_init()
131 if (pci->msi) in nvkm_pci_init()
144 if (pci->msi) in nvkm_pci_dtor()
187 pci->msi = true; in nvkm_pci_new_()
193 pci->msi = false; in nvkm_pci_new_()
196 pci->msi = nvkm_boolopt(device->cfgopt, "NvMSI", pci->msi); in nvkm_pci_new_()
197 if (pci->msi && func->msi_rearm) { in nvkm_pci_new_()
198 pci->msi = pci_enable_msi(pci->pdev) == 0; in nvkm_pci_new_()
199 if (pci->msi) in nvkm_pci_new_()
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-platform-msi-laptop1 What: /sys/devices/platform/msi-laptop-pf/lcd_level
8 What: /sys/devices/platform/msi-laptop-pf/auto_brightness
17 What: /sys/devices/platform/msi-laptop-pf/wlan
24 What: /sys/devices/platform/msi-laptop-pf/bluetooth
33 What: /sys/devices/platform/msi-laptop-pf/touchpad
41 What: /sys/devices/platform/msi-laptop-pf/turbo_mode
54 What: /sys/devices/platform/msi-laptop-pf/eco_mode
64 What: /sys/devices/platform/msi-laptop-pf/turbo_cooldown
75 What: /sys/devices/platform/msi-laptop-pf/auto_fan
/linux/drivers/irqchip/
H A Dirq-riscv-aplic-msi.c15 #include <linux/msi.h>
61 * when APLIC is in MSI mode. in aplic_msi_irq_eoi()
74 * requires interrupt retriggering when APLIC is in MSI mode. in aplic_msi_irq_set_type()
88 /* For zeroed MSI, simply write zero into the target register */ in aplic_msi_write_msg()
99 /* Compute target MSI address */ in aplic_msi_write_msg()
148 .name = "APLIC-MSI",
196 * The APLIC outgoing MSI config registers assume target MSI in aplic_msi_setup()
248 /* Set the APLIC device MSI domain if not available */ in aplic_msi_setup()
251 * The device MSI domain for OF devices is only set at the in aplic_msi_setup()
252 * time of populating/creating OF device. If the device MSI in aplic_msi_setup()
[all …]

12345678910>>...32