Lines Matching full:msi
48 * o Extended Message Signaled Interrupts (MSI-X)
49 * o Message Signaled Interrupts (MSI)
52 * Generally speaking the hardware logically handles MSI and INTx the same and
54 * case. With MSI-X available, each physical function of the device provides the
62 * interrupts is always bound to MSI-X vector zero. Next, we spread out all of
71 * The hardware provides the means of mapping various queues to MSI-X interrupts
94 * any MSI-X to the system. In such a world, there is only one transmit/receive
102 * QINT_TQCTL and QINT_RQCTL registers have a field, 'MSI-X 0 index' which
110 * end up enabling it on the queue registers rather than on the MSI-X registers.
111 * In the MSI-X world, because they can be enabled and disabled, this is
118 * one of the other MSI-X registers.
191 * on interrupt zero and the same is true if we're not using MSI-X. in i40e_intr_set_itr()
207 * However when MSI-X interrupts are not being used, then this also enables and
265 * When MSI-X interrupts are being used, then we can enable the actual
293 * When MSI-X interrupts are being used, then we can disable the actual
487 * Set up a single queue to share the admin queue interrupt in the non-MSI-X
489 * don't have any other vector of control here, unlike with the MSI-X interrupt
603 * change this if MSI-X are actually on the scene. in i40e_intr_chip_init()
774 * Handle an MSI-X interrupt. See section 7.5.1.3 for an overview of
775 * the MSI-X interrupt sequence.
786 * When using MSI-X interrupts, vector 0 is always reserved for the in i40e_intr_msix()