Lines Matching full:msi

615 #define	PCI_CAP_ID_MSI		0x5	/* MSI supported */
627 #define	PCI_CAP_ID_MSI_X	0x11	/* MSI-X supported */
915  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
917 #define	PCI_MSI_CTRL		0x02	/* MSI control register, 2 bytes */
918 #define	PCI_MSI_ADDR_OFFSET	0x04	/* MSI 32-bit msg address, 4 bytes */
919 #define	PCI_MSI_32BIT_DATA	0x08	/* MSI 32-bit msg data, 2 bytes */
920 #define	PCI_MSI_32BIT_EXTDATA	0x0A	/* MSI 32-bit msg ext data, 2 bytes */
921 #define	PCI_MSI_32BIT_MASK	0x0C	/* MSI 32-bit mask bits, 4 bytes */
922 #define	PCI_MSI_32BIT_PENDING	0x10	/* MSI 32-bit pending bits, 4 bytes */
925  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
927 #define	PCI_MSI_64BIT_ADDR	0x08	/* MSI 64-bit upper address, 4 bytes */
928 #define	PCI_MSI_64BIT_DATA	0x0C	/* MSI 64-bit msg data, 2 bytes */
929 #define	PCI_MSI_64BIT_EXTDATA	0x0E	/* MSI 64-bit msg ext data, 2 bytes */
930 #define	PCI_MSI_64BIT_MASKBITS	0x10	/* MSI 64-bit mask bits, 4 bytes */
931 #define	PCI_MSI_64BIT_PENDING	0x14	/* MSI 64-bit pending bits, 4 bytes */
934  * PCI Message Signalled Interrupts (MSI) capability masks and shifts
936 #define	PCI_MSI_ENABLE_BIT	0x0001	/* MSI enable mask in MSI ctrl reg */
937 #define	PCI_MSI_MMC_MASK	0x000E	/* MMC mask in MSI ctrl reg */
939 #define	PCI_MSI_MME_MASK	0x0070	/* MME mask in MSI ctrl reg */
941 #define	PCI_MSI_64BIT_MASK	0x0080	/* 64bit support mask in MSI ctrl reg */
942 #define	PCI_MSI_PVM_MASK	0x0100	/* PVM support mask in MSI ctrl reg */
947  * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
949 #define	PCI_MSIX_CTRL		0x02	/* MSI-X control register, 2 bytes */
950 #define	PCI_MSIX_TBL_OFFSET	0x04	/* MSI-X table offset, 4 bytes */
951 #define	PCI_MSIX_TBL_BIR_MASK	0x0007	/* MSI-X table BIR mask */
952 #define	PCI_MSIX_PBA_OFFSET	0x08	/* MSI-X pending bit array, 4 bytes */
953 #define	PCI_MSIX_PBA_BIR_MASK	0x0007	/* MSI-X PBA BIR mask */
955 #define	PCI_MSIX_TBL_SIZE_MASK	0x07FF	/* table size mask in MSI-X ctrl reg */
956 #define	PCI_MSIX_FUNCTION_MASK	0x4000	/* function mask in MSI-X ctrl reg */
957 #define	PCI_MSIX_ENABLE_BIT	0x8000	/* MSI-X enable mask in MSI-X ctl reg */
959 #define	PCI_MSIX_LOWER_ADDR_OFFSET	0	/* MSI-X lower addr offset */
960 #define	PCI_MSIX_UPPER_ADDR_OFFSET	4	/* MSI-X upper addr offset */
961 #define	PCI_MSIX_DATA_OFFSET		8	/* MSI-X data offset */
962 #define	PCI_MSIX_VECTOR_CTRL_OFFSET	12	/* MSI-X vector ctrl offset */
963 #define	PCI_MSIX_VECTOR_SIZE		16	/* MSI-X size of each vector */
968 #define	PCI_MSI_MAX_INTRS	32	/* maximum MSI interrupts supported */
969 #define	PCI_MSIX_MAX_INTRS	2048	/* maximum MSI-X interrupts supported */