Searched +full:mps2 +full:- +full:uart (Results 1 – 6 of 6) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/serial/arm,mps2-uart.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Arm MPS2 UART10 - Vladimir Murzin <vladimir.murzin@arm.com>13 - $ref: /schemas/serial/serial.yaml#17 const: arm,mps2-uart24 - description: RX interrupt25 - description: TX interrupt[all …]
6 * This file is dual-licensed: you can use it either under the terms45 #include "../armv7-m.dtsi"48 #address-cells = <1>;49 #size-cells = <1>;51 oscclk0: clock-50000000 {52 compatible = "fixed-clock";53 #clock-cells = <0>;54 clock-frequency = <50000000>;57 oscclk1: clock-24576000 {58 compatible = "fixed-clock";[all …]
1 // SPDX-License-Identifier: GPL-2.03 * MPS2 UART driver27 #define DRIVER_NAME "mps2-uart"87 writeb(val, mps_port->port.membase + off); in mps2_uart_write8()94 return readb(mps_port->port.membase + off); in mps2_uart_read8()101 writel_relaxed(val, mps_port->port.membase + off); in mps2_uart_write32()147 * We've just unmasked the TX IRQ and now slow-starting via in mps2_uart_start_tx()150 * point we switch to fully interrupt-driven TX. in mps2_uart_start_tx()171 struct tty_port *tport = &port->state->port; in mps2_uart_rx_chars()176 port->icount.rx++; in mps2_uart_rx_chars()[all …]
1 # SPDX-License-Identifier: GPL-2.06 obj-$(CONFIG_SERIAL_CORE) += serial_base.o7 serial_base-y := serial_core.o serial_base_bus.o serial_ctrl.o serial_port.o9 obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o10 obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o11 obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o16 obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o17 obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o18 obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o19 obj-$(CONFIG_SERIAL_SUNSU) += sunsu.o[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */19 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */20 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */21 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */22 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */23 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */24 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */25 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */29 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */30 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */[all …]
5 ---------------------------------------------------21 W: *Web-page* with status/info23 B: URI for where to file *bugs*. A web-page with detailed bug28 patches to the given subsystem. This is either an in-tree file,29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst46 N: [^a-z]tegra all files whose path contains tegra64 ----------------83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)85 L: linux-scsi@vger.kernel.org88 F: drivers/scsi/3w-*[all …]