Home
last modified time | relevance | path

Searched +full:mpic +full:- +full:msi (Results 1 – 25 of 37) sorted by relevance

12

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,mpic-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
11 -------------------------------------------
14 Freescale MSI driver calculates the address of MSIIR (in the MSI register
15 block) and sets that address as the MSI message address.
39 this. The address specified in the msi-address-64 property is the PCI
[all …]
H A Dmarvell,mpic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
14 platforms it also provides inter-processor interrupts.
18 Provides MSI handling for the PCIe controllers.
22 const: marvell,mpic
26 - description: main registers
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8641si-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
22 mcm-law@0 {
[all …]
H A Dqoriq-mpic.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
35 mpic: pic@40000 { label
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
40 compatible = "fsl,mpic", "chrp,open-pic";
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
46 compatible = "fsl,mpic-global-timer";
54 msi0: msi@41600 {
[all …]
H A Dqoriq-mpic4.3.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
35 mpic: pic@40000 { label
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
40 compatible = "fsl,mpic";
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
46 compatible = "fsl,mpic-global-timer";
54 msi0: msi@41600 {
[all …]
H A Dpq3-mpic.dtsi2 * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ]
35 mpic: pic@40000 { label
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
40 compatible = "fsl,mpic";
41 device_type = "open-pic";
42 big-endian;
43 single-cpu-affinity;
44 last-interrupt-source = <255>;
[all …]
H A Dp1020rdb-pc_camp_core1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * P1020 RDB-PC Core1 Device Tree Source in CAMP mode.
5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
9 * Please note to add "-b 1" for core1's dts compiling.
14 /include/ "p1020rdb-pc_32b.dts"
17 model = "fsl,P1020RDB-PC";
18 compatible = "fsl,P1020RDB-PC";
40 ecm-law@0 {
48 memory-controller@2000 {
68 gpio: gpio-controller@f000 {
[all …]
H A Dp1020rdb-pc_camp_core0.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * P1020 RDB-PC Core0 Device Tree Source in CAMP mode.
5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
8 * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
10 * Please note to add "-b 0" for core0's dts compiling.
15 /include/ "p1020rdb-pc_32b.dts"
18 model = "fsl,P1020RDB-PC";
19 compatible = "fsl,P1020RDB-PC";
52 mpic: pic@40000 { label
53 protected-sources = <
[all …]
H A Dmpc8572ds_camp_core0.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
7 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
10 * Copyright 2007-2009 Freescale Semiconductor Inc.
17 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
38 gpio-controller@f000 {
40 l2-cache-controller@20000 {
41 cache-size = <0x80000>; // L2, 512K
56 protected-sources = <
59 0xe4 0xe5 0xe6 0xe7 /* msi */
[all …]
H A Dmpc8572ds_camp_core1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
7 * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
9 * Please note to add "-b 1" for core1's dts compiling.
11 * Copyright 2007-2009 Freescale Semiconductor Inc.
18 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
33 ecm-law@0 {
39 memory-controller@2000 {
42 memory-controller@6000 {
54 gpio-controller@f000 {
[all …]
/linux/drivers/irqchip/
H A Dirq-armada-370-xp.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
23 #include <linux/irqchip/irq-msi-lib.h>
32 #include <linux/msi.h>
46 * +---------------+ +---------------+
48 * | per-CPU | | per-CPU |
52 * +---------------+ +---------------+
57 * +-------------------+
62 * +-------------------+
[all …]
/linux/arch/powerpc/platforms/pasemi/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
13 #include <linux/msi.h>
14 #include <asm/mpic.h>
16 #include <asm/ppc-pci.h>
19 #include <sysdev/mpic.h>
23 * needs more than 32 MSI's down the road we'll have to rethink this,
31 static struct mpic *msi_mpic;
36 pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq); in mpic_pasemi_msi_mask_irq()
43 pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq); in mpic_pasemi_msi_unmask_irq()
[all …]
/linux/arch/powerpc/sysdev/
H A Dmpic_u3msi.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
9 #include <linux/msi.h>
10 #include <asm/mpic.h>
12 #include <asm/ppc-pci.h>
15 #include "mpic.h"
18 static struct mpic *msi_mpic;
39 .name = "MPIC-U3MSI",
66 for (bus = pdev->bus; bus && bus->self; bus = bus->parent) { in find_ht_magic_addr()
67 pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING); in find_ht_magic_addr()
[all …]
H A Dmpic_msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
10 #include <linux/msi.h>
11 #include <asm/mpic.h>
13 #include <asm/ppc-pci.h>
16 #include <sysdev/mpic.h>
18 void mpic_msi_reserve_hwirq(struct mpic *mpic, irq_hw_number_t hwirq) in mpic_msi_reserve_hwirq() argument
20 /* The mpic calls this even when there is no allocator setup */ in mpic_msi_reserve_hwirq()
21 if (!mpic->msi_bitmap.bitmap) in mpic_msi_reserve_hwirq()
24 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, hwirq); in mpic_msi_reserve_hwirq()
[all …]
H A Dfsl_msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
11 #include <linux/msi.h>
24 #include <asm/ppc-pci.h>
25 #include <asm/mpic.h>
39 #define msi_hwirq(msi, msir_index, intr_index) \ argument
40 ((msir_index) << (msi)->srs_shift | \
41 ((intr_index) << (msi)->ibs_shift))
63 * in the cascade interrupt. So, this MSI interrupt has been acked
71 struct fsl_msi *msi_data = irqd->domain->host_data; in fsl_msi_print_chip()
[all …]
/linux/arch/powerpc/boot/dts/
H A Dakebono.dts12 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
H A Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5370.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
34 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5330.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
/linux/arch/powerpc/kvm/
H A Dmpic.c33 #include <asm/mpic.h>
44 #define VID 0x03 /* MPIC version ID */
63 #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000))
116 struct kvm_vcpu *vcpu = current->thread.kvm_vcpu; in get_current_cpu()
117 return vcpu ? vcpu->arch.irq_cpu_id : -1; in get_current_cpu()
120 return -1; in get_current_cpu()
133 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
154 bool level:1; /* level-triggered */
171 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
173 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dmarvell,kirkwood-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/marvell,kirkwood-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
11 - Pali Rohár <pali@kernel.org>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - marvell,armada-370-pcie
20 - marvell,armada-xp-pcie
21 - marvell,dove-pcie
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-39x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
37 compatible = "arm,cortex-a9";
[all …]
H A Darmada-375.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
[all …]

12