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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmsi-pic.txt1 * Freescale MSI interrupt controller
4 - compatible : compatible list, may contain one or two entries
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
13 - reg : It may contain one or two regions. The first region should contain
17 region must be added because different MSI group has different MSIIR1 offset.
19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dfsl,mpic-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
11 -------------------------------------------
14 Freescale MSI driver calculates the address of MSIIR (in the MSI register
15 block) and sets that address as the MSI message address.
39 this. The address specified in the msi-address-64 property is the PCI
[all …]
H A Dmarvell,mpic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
14 platforms it also provides inter-processor interrupts.
18 Provides MSI handling for the PCIe controllers.
22 const: marvell,mpic
26 - description: main registers
[all …]
H A Dmarvell,armada-370-xp-mpic.txt2 -----------------------------------------------------
5 - compatible: Should be "marvell,mpic"
6 - interrupt-controller: Identifies the node as an interrupt controller.
7 - msi-controller: Identifies the node as an PCI Message Signaled
9 - #interrupt-cells: The number of cells to define the interrupts. Should be 1.
12 - reg: Should contain PMIC registers location and length. First pair
13 for the main interrupt registers, second pair for the per-CPU
21 - interrupts: If defined, then it indicates that this MPIC is
23 typically the case on Armada 375 and Armada 38x, where the MPIC is
24 connected as a slave to the Cortex-A9 GIC. The provided interrupt
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8641si-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
22 mcm-law@0 {
[all …]
H A Dqoriq-mpic.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
35 mpic: pic@40000 { label
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
40 compatible = "fsl,mpic", "chrp,open-pic";
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
46 compatible = "fsl,mpic-global-timer";
54 msi0: msi@41600 {
[all …]
H A Dqoriq-mpic4.3.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
35 mpic: pic@40000 { label
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
40 compatible = "fsl,mpic";
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
46 compatible = "fsl,mpic-global-timer";
54 msi0: msi@41600 {
[all …]
H A Dpq3-mpic.dtsi2 * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ]
35 mpic: pic@40000 { label
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
40 compatible = "fsl,mpic";
41 device_type = "open-pic";
42 big-endian;
43 single-cpu-affinity;
44 last-interrupt-source = <255>;
[all …]
H A Dp1020rdb-pc_camp_core1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * P1020 RDB-PC Core1 Device Tree Source in CAMP mode.
5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
9 * Please note to add "-b 1" for core1's dts compiling.
14 /include/ "p1020rdb-pc_32b.dts"
17 model = "fsl,P1020RDB-PC";
18 compatible = "fsl,P1020RDB-PC";
40 ecm-law@0 {
48 memory-controller@2000 {
68 gpio: gpio-controller@f000 {
[all …]
H A Dp1020rdb-pc_camp_core0.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * P1020 RDB-PC Core0 Device Tree Source in CAMP mode.
5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
8 * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
10 * Please note to add "-b 0" for core0's dts compiling.
15 /include/ "p1020rdb-pc_32b.dts"
18 model = "fsl,P1020RDB-PC";
19 compatible = "fsl,P1020RDB-PC";
52 mpic: pic@40000 { label
53 protected-sources = <
[all …]
H A Dmpc8572ds_camp_core0.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
7 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
10 * Copyright 2007-2009 Freescale Semiconductor Inc.
17 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
38 gpio-controller@f000 {
40 l2-cache-controller@20000 {
41 cache-size = <0x80000>; // L2, 512K
56 protected-sources = <
59 0xe4 0xe5 0xe6 0xe7 /* msi */
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dakebono.dts12 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
H A Dmpc8610_hpcd.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <32768>; // L1
[all …]
H A Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5370.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
34 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5330.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
/freebsd/sys/dts/powerpc/
H A Dp3041si.dtsi4 * Copyright 2010-2011 Freescale Semiconductor Inc.
35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
102 #address-cells = <1>;
103 #size-cells = <0>;
108 bus-frequency = <749999996>;
109 next-level-cache = <&L2_0>;
110 L2_0: l2-cache {
[all …]
H A Dp1020rdb.dts35 /dts-v1/;
40 #address-cells = <2>;
41 #size-cells = <2>;
54 #address-cells = <1>;
55 #size-cells = <0>;
60 next-level-cache = <&L2>;
66 next-level-cache = <&L2>;
75 #address-cells = <2>;
76 #size-cells = <1>;
77 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
[all …]
H A Dp5020si.dtsi4 * Copyright 2010-2011 Freescale Semiconductor Inc.
35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
108 #address-cells = <1>;
109 #size-cells = <0>;
114 bus-frequency = <799999998>;
115 next-level-cache = <&L2_0>;
116 L2_0: l2-cache {
[all …]
H A Dmpc8572ds.dts4 * Copyright 2007-2009 Freescale Semiconductor Inc. All rights reserved
55 * MA 02110-1301, USA.
58 *------------------------------------------------------------------
61 /dts-v1/;
65 #address-cells = <2>;
66 #size-cells = <2>;
81 #address-cells = <1>;
82 #size-cells = <0>;
87 d-cache-line-size = <32>; // 32 bytes
88 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dp2041si.dtsi35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
101 #address-cells = <1>;
102 #size-cells = <0>;
107 bus-frequency = <749999996>;
108 next-level-cache = <&L2_0>;
109 L2_0: l2-cache {
110 next-level-cache = <&cpc>;
[all …]
H A Dp2020ds.dts55 * MA 02110-1301, USA.
58 *------------------------------------------------------------------
61 /dts-v1/;
65 #address-cells = <2>;
66 #size-cells = <2>;
80 #address-cells = <1>;
81 #size-cells = <0>;
86 next-level-cache = <&L2>;
92 next-level-cache = <&L2>;
101 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dmarvell,kirkwood-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/marvell,kirkwood-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
11 - Pali Rohár <pali@kernel.org>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - marvell,armada-370-pcie
20 - marvell,armada-xp-pcie
21 - marvell,dove-pcie
[all …]
H A Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]

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