1/* 2 * P2020 DS Device Tree Source 3 * 4 * Copyright 2009 Freescale Semiconductor Inc. 5 * 6 * Neither the name of Freescale Semiconductor, Inc nor the names of 7 * its contributors may be used to endorse or promote products derived 8 * from this software without specific prior written permission. 9 * 10 * Freescale hereby publishes it under the following licenses: 11 * 12 * BSD License 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 21 * Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in 23 * the documentation and/or other materials provided with the 24 * distribution. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 27 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 33 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 35 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * GNU General Public License, version 2 41 * 42 * This program is free software; you can redistribute it and/or 43 * modify it under the terms of the GNU General Public License 44 * as published by the Free Software Foundation; either version 2 45 * of the License, or (at your option) any later version. 46 * 47 * This program is distributed in the hope that it will be useful, 48 * but WITHOUT ANY WARRANTY; without even the implied warranty of 49 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 50 * GNU General Public License for more details. 51 * 52 * You should have received a copy of the GNU General Public License 53 * along with this program; if not, write to the Free Software 54 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 55 * MA 02110-1301, USA. 56 * 57 * You may select the license of your choice. 58 *------------------------------------------------------------------ 59 */ 60 61/dts-v1/; 62/ { 63 model = "fsl,P2020"; 64 compatible = "fsl,P2020DS"; 65 #address-cells = <2>; 66 #size-cells = <2>; 67 68 aliases { 69 ethernet0 = &enet0; 70 ethernet1 = &enet1; 71 ethernet2 = &enet2; 72 serial0 = &serial0; 73 serial1 = &serial1; 74 pci0 = &pci0; 75 pci1 = &pci1; 76 pci2 = &pci2; 77 }; 78 79 cpus { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 PowerPC,P2020@0 { 84 device_type = "cpu"; 85 reg = <0x0>; 86 next-level-cache = <&L2>; 87 }; 88 89 PowerPC,P2020@1 { 90 device_type = "cpu"; 91 reg = <0x1>; 92 next-level-cache = <&L2>; 93 }; 94 }; 95 96 memory { 97 device_type = "memory"; 98 }; 99 100 localbus@ffe05000 { 101 #address-cells = <2>; 102 #size-cells = <1>; 103 compatible = "fsl,elbc", "simple-bus"; 104 reg = <0 0xffe05000 0 0x1000>; 105 interrupts = <19 2>; 106 interrupt-parent = <&mpic>; 107 108 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 109 0x1 0x0 0x0 0xe0000000 0x08000000 110 0x2 0x0 0x0 0xffa00000 0x00040000 111 0x3 0x0 0x0 0xffdf0000 0x00008000 112 0x4 0x0 0x0 0xffa40000 0x00040000 113 0x5 0x0 0x0 0xffa80000 0x00040000 114 0x6 0x0 0x0 0xffac0000 0x00040000>; 115 116 nor@0,0 { 117 #address-cells = <1>; 118 #size-cells = <1>; 119 compatible = "cfi-flash"; 120 reg = <0x0 0x0 0x8000000>; 121 bank-width = <2>; 122 device-width = <1>; 123 124 ramdisk@0 { 125 reg = <0x0 0x03000000>; 126 read-only; 127 }; 128 129 diagnostic@3000000 { 130 reg = <0x03000000 0x00e00000>; 131 read-only; 132 }; 133 134 dink@3e00000 { 135 reg = <0x03e00000 0x00200000>; 136 read-only; 137 }; 138 139 kernel@4000000 { 140 reg = <0x04000000 0x00400000>; 141 read-only; 142 }; 143 144 jffs2@4400000 { 145 reg = <0x04400000 0x03b00000>; 146 }; 147 148 dtb@7f00000 { 149 reg = <0x07f00000 0x00080000>; 150 read-only; 151 }; 152 153 u-boot@7f80000 { 154 reg = <0x07f80000 0x00080000>; 155 read-only; 156 }; 157 }; 158 159 nand@2,0 { 160 #address-cells = <1>; 161 #size-cells = <1>; 162 compatible = "fsl,elbc-fcm-nand"; 163 reg = <0x2 0x0 0x40000>; 164 165 u-boot@0 { 166 reg = <0x0 0x02000000>; 167 read-only; 168 }; 169 170 jffs2@2000000 { 171 reg = <0x02000000 0x10000000>; 172 }; 173 174 ramdisk@12000000 { 175 reg = <0x12000000 0x08000000>; 176 read-only; 177 }; 178 179 kernel@1a000000 { 180 reg = <0x1a000000 0x04000000>; 181 }; 182 183 dtb@1e000000 { 184 reg = <0x1e000000 0x01000000>; 185 read-only; 186 }; 187 188 empty@1f000000 { 189 reg = <0x1f000000 0x21000000>; 190 }; 191 }; 192 193 nand@4,0 { 194 compatible = "fsl,elbc-fcm-nand"; 195 reg = <0x4 0x0 0x40000>; 196 }; 197 198 nand@5,0 { 199 compatible = "fsl,elbc-fcm-nand"; 200 reg = <0x5 0x0 0x40000>; 201 }; 202 203 nand@6,0 { 204 compatible = "fsl,elbc-fcm-nand"; 205 reg = <0x6 0x0 0x40000>; 206 }; 207 }; 208 209 soc@ffe00000 { 210 #address-cells = <1>; 211 #size-cells = <1>; 212 device_type = "soc"; 213 compatible = "fsl,p2020-immr", "simple-bus"; 214 ranges = <0x0 0 0xffe00000 0x100000>; 215 bus-frequency = <0>; // Filled out by uboot. 216 217 ecm-law@0 { 218 compatible = "fsl,ecm-law"; 219 reg = <0x0 0x1000>; 220 fsl,num-laws = <12>; 221 }; 222 223 ecm@1000 { 224 compatible = "fsl,p2020-ecm", "fsl,ecm"; 225 reg = <0x1000 0x1000>; 226 interrupts = <17 2>; 227 interrupt-parent = <&mpic>; 228 }; 229 230 memory-controller@2000 { 231 compatible = "fsl,p2020-memory-controller"; 232 reg = <0x2000 0x1000>; 233 interrupt-parent = <&mpic>; 234 interrupts = <18 2>; 235 }; 236 237 i2c@3000 { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 cell-index = <0>; 241 compatible = "fsl-i2c"; 242 reg = <0x3000 0x100>; 243 interrupts = <43 2>; 244 interrupt-parent = <&mpic>; 245 dfsrr; 246 }; 247 248 i2c@3100 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 cell-index = <1>; 252 compatible = "fsl-i2c"; 253 reg = <0x3100 0x100>; 254 interrupts = <43 2>; 255 interrupt-parent = <&mpic>; 256 dfsrr; 257 }; 258 259 serial0: serial@4500 { 260 cell-index = <0>; 261 device_type = "serial"; 262 compatible = "ns16550"; 263 reg = <0x4500 0x100>; 264 clock-frequency = <0>; 265 interrupts = <42 2>; 266 interrupt-parent = <&mpic>; 267 }; 268 269 serial1: serial@4600 { 270 cell-index = <1>; 271 device_type = "serial"; 272 compatible = "ns16550"; 273 reg = <0x4600 0x100>; 274 clock-frequency = <0>; 275 interrupts = <42 2>; 276 interrupt-parent = <&mpic>; 277 }; 278 279 spi@7000 { 280 compatible = "fsl,espi"; 281 reg = <0x7000 0x1000>; 282 interrupts = <59 0x2>; 283 interrupt-parent = <&mpic>; 284 }; 285 286 dma@c300 { 287 #address-cells = <1>; 288 #size-cells = <1>; 289 compatible = "fsl,eloplus-dma"; 290 reg = <0xc300 0x4>; 291 ranges = <0x0 0xc100 0x200>; 292 cell-index = <1>; 293 dma-channel@0 { 294 compatible = "fsl,eloplus-dma-channel"; 295 reg = <0x0 0x80>; 296 cell-index = <0>; 297 interrupt-parent = <&mpic>; 298 interrupts = <76 2>; 299 }; 300 dma-channel@80 { 301 compatible = "fsl,eloplus-dma-channel"; 302 reg = <0x80 0x80>; 303 cell-index = <1>; 304 interrupt-parent = <&mpic>; 305 interrupts = <77 2>; 306 }; 307 dma-channel@100 { 308 compatible = "fsl,eloplus-dma-channel"; 309 reg = <0x100 0x80>; 310 cell-index = <2>; 311 interrupt-parent = <&mpic>; 312 interrupts = <78 2>; 313 }; 314 dma-channel@180 { 315 compatible = "fsl,eloplus-dma-channel"; 316 reg = <0x180 0x80>; 317 cell-index = <3>; 318 interrupt-parent = <&mpic>; 319 interrupts = <79 2>; 320 }; 321 }; 322 323 gpio: gpio-controller@f000 { 324 #gpio-cells = <2>; 325 compatible = "fsl,mpc8572-gpio"; 326 reg = <0xf000 0x100>; 327 interrupts = <47 0x2>; 328 interrupt-parent = <&mpic>; 329 gpio-controller; 330 }; 331 332 L2: l2-cache-controller@20000 { 333 compatible = "fsl,p2020-l2-cache-controller"; 334 reg = <0x20000 0x1000>; 335 cache-line-size = <32>; // 32 bytes 336 cache-size = <0x80000>; // L2, 512k 337 interrupt-parent = <&mpic>; 338 interrupts = <16 2>; 339 }; 340 341 dma@21300 { 342 #address-cells = <1>; 343 #size-cells = <1>; 344 compatible = "fsl,eloplus-dma"; 345 reg = <0x21300 0x4>; 346 ranges = <0x0 0x21100 0x200>; 347 cell-index = <0>; 348 dma-channel@0 { 349 compatible = "fsl,eloplus-dma-channel"; 350 reg = <0x0 0x80>; 351 cell-index = <0>; 352 interrupt-parent = <&mpic>; 353 interrupts = <20 2>; 354 }; 355 dma-channel@80 { 356 compatible = "fsl,eloplus-dma-channel"; 357 reg = <0x80 0x80>; 358 cell-index = <1>; 359 interrupt-parent = <&mpic>; 360 interrupts = <21 2>; 361 }; 362 dma-channel@100 { 363 compatible = "fsl,eloplus-dma-channel"; 364 reg = <0x100 0x80>; 365 cell-index = <2>; 366 interrupt-parent = <&mpic>; 367 interrupts = <22 2>; 368 }; 369 dma-channel@180 { 370 compatible = "fsl,eloplus-dma-channel"; 371 reg = <0x180 0x80>; 372 cell-index = <3>; 373 interrupt-parent = <&mpic>; 374 interrupts = <23 2>; 375 }; 376 }; 377 378 usb@22000 { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 compatible = "fsl-usb2-dr"; 382 reg = <0x22000 0x1000>; 383 interrupt-parent = <&mpic>; 384 interrupts = <28 0x2>; 385 phy_type = "ulpi"; 386 }; 387 388 enet0: ethernet@24000 { 389 #address-cells = <1>; 390 #size-cells = <1>; 391 cell-index = <0>; 392 device_type = "network"; 393 model = "eTSEC"; 394 compatible = "gianfar"; 395 reg = <0x24000 0x1000>; 396 ranges = <0x0 0x24000 0x1000>; 397 local-mac-address = [ 00 00 00 00 00 00 ]; 398 interrupts = <29 2 30 2 34 2>; 399 interrupt-parent = <&mpic>; 400 tbi-handle = <&tbi0>; 401 phy-handle = <&phy0>; 402 phy-connection-type = "rgmii-id"; 403 404 mdio@520 { 405 #address-cells = <1>; 406 #size-cells = <0>; 407 compatible = "fsl,gianfar-mdio"; 408 reg = <0x520 0x20>; 409 410 phy0: ethernet-phy@0 { 411 interrupt-parent = <&mpic>; 412 interrupts = <3 1>; 413 reg = <0x0>; 414 }; 415 phy1: ethernet-phy@1 { 416 interrupt-parent = <&mpic>; 417 interrupts = <3 1>; 418 reg = <0x1>; 419 }; 420 phy2: ethernet-phy@2 { 421 interrupt-parent = <&mpic>; 422 interrupts = <3 1>; 423 reg = <0x2>; 424 }; 425 tbi0: tbi-phy@11 { 426 reg = <0x11>; 427 device_type = "tbi-phy"; 428 }; 429 }; 430 }; 431 432 enet1: ethernet@25000 { 433 #address-cells = <1>; 434 #size-cells = <1>; 435 cell-index = <1>; 436 device_type = "network"; 437 model = "eTSEC"; 438 compatible = "gianfar"; 439 reg = <0x25000 0x1000>; 440 ranges = <0x0 0x25000 0x1000>; 441 local-mac-address = [ 00 00 00 00 00 00 ]; 442 interrupts = <35 2 36 2 40 2>; 443 interrupt-parent = <&mpic>; 444 tbi-handle = <&tbi1>; 445 phy-handle = <&phy1>; 446 phy-connection-type = "rgmii-id"; 447 448 mdio@520 { 449 #address-cells = <1>; 450 #size-cells = <0>; 451 compatible = "fsl,gianfar-tbi"; 452 reg = <0x520 0x20>; 453 454 tbi1: tbi-phy@11 { 455 reg = <0x11>; 456 device_type = "tbi-phy"; 457 }; 458 }; 459 }; 460 461 enet2: ethernet@26000 { 462 #address-cells = <1>; 463 #size-cells = <1>; 464 cell-index = <2>; 465 device_type = "network"; 466 model = "eTSEC"; 467 compatible = "gianfar"; 468 reg = <0x26000 0x1000>; 469 ranges = <0x0 0x26000 0x1000>; 470 local-mac-address = [ 00 00 00 00 00 00 ]; 471 interrupts = <31 2 32 2 33 2>; 472 interrupt-parent = <&mpic>; 473 tbi-handle = <&tbi2>; 474 phy-handle = <&phy2>; 475 phy-connection-type = "rgmii-id"; 476 477 mdio@520 { 478 #address-cells = <1>; 479 #size-cells = <0>; 480 compatible = "fsl,gianfar-tbi"; 481 reg = <0x520 0x20>; 482 483 tbi2: tbi-phy@11 { 484 reg = <0x11>; 485 device_type = "tbi-phy"; 486 }; 487 }; 488 }; 489 490 sdhci@2e000 { 491 compatible = "fsl,p2020-esdhc", "fsl,esdhc"; 492 reg = <0x2e000 0x1000>; 493 interrupts = <72 0x2>; 494 interrupt-parent = <&mpic>; 495 /* Filled in by U-Boot */ 496 clock-frequency = <0>; 497 }; 498 499 crypto@30000 { 500 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", 501 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; 502 reg = <0x30000 0x10000>; 503 interrupts = <45 2 58 2>; 504 interrupt-parent = <&mpic>; 505 fsl,num-channels = <4>; 506 fsl,channel-fifo-len = <24>; 507 fsl,exec-units-mask = <0xbfe>; 508 fsl,descriptor-types-mask = <0x3ab0ebf>; 509 }; 510 511 mpic: pic@40000 { 512 interrupt-controller; 513 #address-cells = <0>; 514 #interrupt-cells = <2>; 515 reg = <0x40000 0x40000>; 516 compatible = "chrp,open-pic"; 517 device_type = "open-pic"; 518 }; 519 520 msi@41600 { 521 compatible = "fsl,mpic-msi"; 522 reg = <0x41600 0x80>; 523 msi-available-ranges = <0 0x100>; 524 interrupts = < 525 0xe0 0 526 0xe1 0 527 0xe2 0 528 0xe3 0 529 0xe4 0 530 0xe5 0 531 0xe6 0 532 0xe7 0>; 533 interrupt-parent = <&mpic>; 534 }; 535 536 global-utilities@e0000 { //global utilities block 537 compatible = "fsl,p2020-guts"; 538 reg = <0xe0000 0x1000>; 539 fsl,has-rstcr; 540 }; 541 }; 542 543 pci0: pcie@ffe08000 { 544 compatible = "fsl,mpc8548-pcie"; 545 device_type = "pci"; 546 #interrupt-cells = <1>; 547 #size-cells = <2>; 548 #address-cells = <3>; 549 reg = <0 0xffe08000 0 0x1000>; 550 bus-range = <0 255>; 551 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 552 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 553 clock-frequency = <33333333>; 554 interrupt-parent = <&mpic>; 555 interrupts = <24 2>; 556 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 557 interrupt-map = < 558 /* IDSEL 0x0 */ 559 0000 0x0 0x0 0x1 &mpic 0x8 0x1 560 0000 0x0 0x0 0x2 &mpic 0x9 0x1 561 0000 0x0 0x0 0x3 &mpic 0xa 0x1 562 0000 0x0 0x0 0x4 &mpic 0xb 0x1 563 >; 564 pcie@0 { 565 reg = <0x0 0x0 0x0 0x0 0x0>; 566 #size-cells = <2>; 567 #address-cells = <3>; 568 device_type = "pci"; 569 ranges = <0x2000000 0x0 0x80000000 570 0x2000000 0x0 0x80000000 571 0x0 0x20000000 572 573 0x1000000 0x0 0x0 574 0x1000000 0x0 0x0 575 0x0 0x10000>; 576 }; 577 }; 578 579 pci1: pcie@ffe09000 { 580 compatible = "fsl,mpc8548-pcie"; 581 device_type = "pci"; 582 #interrupt-cells = <1>; 583 #size-cells = <2>; 584 #address-cells = <3>; 585 reg = <0 0xffe09000 0 0x1000>; 586 bus-range = <0 255>; 587 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 588 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 589 clock-frequency = <33333333>; 590 interrupt-parent = <&mpic>; 591 interrupts = <25 2>; 592 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 593 interrupt-map = < 594 595 // IDSEL 0x11 func 0 - PCI slot 1 596 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2 597 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2 598 599 // IDSEL 0x11 func 1 - PCI slot 1 600 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2 601 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2 602 603 // IDSEL 0x11 func 2 - PCI slot 1 604 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2 605 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2 606 607 // IDSEL 0x11 func 3 - PCI slot 1 608 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2 609 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2 610 611 // IDSEL 0x11 func 4 - PCI slot 1 612 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2 613 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2 614 615 // IDSEL 0x11 func 5 - PCI slot 1 616 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2 617 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2 618 619 // IDSEL 0x11 func 6 - PCI slot 1 620 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2 621 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2 622 623 // IDSEL 0x11 func 7 - PCI slot 1 624 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2 625 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2 626 627 // IDSEL 0x1d Audio 628 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 629 630 // IDSEL 0x1e Legacy 631 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 632 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 633 634 // IDSEL 0x1f IDE/SATA 635 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 636 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 637 >; 638 639 pcie@0 { 640 reg = <0x0 0x0 0x0 0x0 0x0>; 641 #size-cells = <2>; 642 #address-cells = <3>; 643 device_type = "pci"; 644 ranges = <0x2000000 0x0 0xa0000000 645 0x2000000 0x0 0xa0000000 646 0x0 0x20000000 647 648 0x1000000 0x0 0x0 649 0x1000000 0x0 0x0 650 0x0 0x10000>; 651 uli1575@0 { 652 reg = <0x0 0x0 0x0 0x0 0x0>; 653 #size-cells = <2>; 654 #address-cells = <3>; 655 ranges = <0x2000000 0x0 0xa0000000 656 0x2000000 0x0 0xa0000000 657 0x0 0x20000000 658 659 0x1000000 0x0 0x0 660 0x1000000 0x0 0x0 661 0x0 0x10000>; 662 isa@1e { 663 device_type = "isa"; 664 #interrupt-cells = <2>; 665 #size-cells = <1>; 666 #address-cells = <2>; 667 reg = <0xf000 0x0 0x0 0x0 0x0>; 668 ranges = <0x1 0x0 0x1000000 0x0 0x0 669 0x1000>; 670 interrupt-parent = <&i8259>; 671 672 i8259: interrupt-controller@20 { 673 reg = <0x1 0x20 0x2 674 0x1 0xa0 0x2 675 0x1 0x4d0 0x2>; 676 interrupt-controller; 677 device_type = "interrupt-controller"; 678 #address-cells = <0>; 679 #interrupt-cells = <2>; 680 compatible = "chrp,iic"; 681 interrupts = <4 1>; 682 interrupt-parent = <&mpic>; 683 }; 684 685 i8042@60 { 686 #size-cells = <0>; 687 #address-cells = <1>; 688 reg = <0x1 0x60 0x1 0x1 0x64 0x1>; 689 interrupts = <1 3 12 3>; 690 interrupt-parent = 691 <&i8259>; 692 693 keyboard@0 { 694 reg = <0x0>; 695 compatible = "pnpPNP,303"; 696 }; 697 698 mouse@1 { 699 reg = <0x1>; 700 compatible = "pnpPNP,f03"; 701 }; 702 }; 703 704 rtc@70 { 705 compatible = "pnpPNP,b00"; 706 reg = <0x1 0x70 0x2>; 707 }; 708 709 gpio@400 { 710 reg = <0x1 0x400 0x80>; 711 }; 712 }; 713 }; 714 }; 715 716 }; 717 718 pci2: pcie@ffe0a000 { 719 compatible = "fsl,mpc8548-pcie"; 720 device_type = "pci"; 721 #interrupt-cells = <1>; 722 #size-cells = <2>; 723 #address-cells = <3>; 724 reg = <0 0xffe0a000 0 0x1000>; 725 bus-range = <0 255>; 726 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 727 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 728 clock-frequency = <33333333>; 729 interrupt-parent = <&mpic>; 730 interrupts = <26 2>; 731 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 732 interrupt-map = < 733 /* IDSEL 0x0 */ 734 0000 0x0 0x0 0x1 &mpic 0x0 0x1 735 0000 0x0 0x0 0x2 &mpic 0x1 0x1 736 0000 0x0 0x0 0x3 &mpic 0x2 0x1 737 0000 0x0 0x0 0x4 &mpic 0x3 0x1 738 >; 739 pcie@0 { 740 reg = <0x0 0x0 0x0 0x0 0x0>; 741 #size-cells = <2>; 742 #address-cells = <3>; 743 device_type = "pci"; 744 ranges = <0x2000000 0x0 0xc0000000 745 0x2000000 0x0 0xc0000000 746 0x0 0x20000000 747 748 0x1000000 0x0 0x0 749 0x1000000 0x0 0x0 750 0x0 0x10000>; 751 }; 752 }; 753}; 754