| /linux/drivers/soc/fsl/qe/ |
| H A D | ucc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * QE UCC API Set - UCC specific routines implementations.
33 if (ucc_num > UCC_MAX_NUM - 1) in ucc_set_qe_mux_mii_mng()
34 return -EINVAL; in ucc_set_qe_mux_mii_mng()
37 qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG, in ucc_set_qe_mux_mii_mng()
50 * 'ucc_num' is the UCC number, from 0 - 7.
61 switch (ucc_num) { in ucc_set_type()
62 case 0: guemr = &qe_immr->ucc1.slow.guemr; in ucc_set_type()
64 case 1: guemr = &qe_immr->ucc2.slow.guemr; in ucc_set_type()
66 case 2: guemr = &qe_immr->ucc3.slow.guemr; in ucc_set_type()
[all …]
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| /linux/drivers/net/dsa/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Distributed Switch Architecture drivers"
8 tristate "Broadcom Starfighter 2 Ethernet switch support"
17 switch chips.
20 tristate "DSA mock-up Ethernet switch chip support"
24 This enables support for a fake mock-up switch chip which
32 tristate "MediaTek MT7530 and MT7531 Ethernet switch support"
39 switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
40 MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
49 This enables support for the MediaTek MT7530 and MT7531 switch
[all …]
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| /linux/Documentation/devicetree/bindings/regulator/ |
| H A D | qcom,rpm-regulator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/qcom,rpm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 The regulator node houses sub-nodes for each regulator within the device.
16 Each sub-node is identified using the node's name, with valid values listed
28 l29, lvs1, lvs2, lvs3, lvs4, lvs5, lvs6, lvs7, usb-switch, hdmi-switch,
37 - Bjorn Andersson <andersson@kernel.org>
42 - qcom,rpm-pm8058-regulators
43 - qcom,rpm-pm8901-regulators
[all …]
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| /linux/drivers/phy/freescale/ |
| H A D | phy-fsl-lynx-10g.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2021-2026 NXP */
13 #include "phy-fsl-lynx-core.h"
28 #define SGMII_CFG(id) (28 - (id) * 4)
29 #define QSGMII_CFG(id) (28 - (id) * 4)
30 #define SXGMII_CFG(id) (28 - (id) * 4)
31 #define QXGMII_CFG(id) (12 - (id) * 4)
32 #define XFI_CFG(id) (28 - (id) * 4)
285 dev_dbg(&lane->phy->dev, in lynx_10g_cdr_lock_check()
287 'A' + lane->id); in lynx_10g_cdr_lock_check()
[all …]
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| /linux/drivers/thunderbolt/ |
| H A D | tmu.c | 1 // SPDX-License-Identifier: GPL-2.0
40 static const char *tmu_mode_name(enum tb_switch_tmu_mode mode) in tmu_mode_name() argument
42 switch (mode) { in tmu_mode_name()
46 return "uni-directional, LowRes"; in tmu_mode_name()
48 return "uni-directional, HiFi"; in tmu_mode_name()
50 return "bi-directional, HiFi"; in tmu_mode_name()
52 return "enhanced uni-directional, MedRes"; in tmu_mode_name()
64 enum tb_switch_tmu_mode mode) in tb_switch_set_tmu_mode_params() argument
69 freq = tmu_params[mode].freq_meas_window; in tb_switch_set_tmu_mode_params()
70 avg = tmu_params[mode].avg_const; in tb_switch_set_tmu_mode_params()
[all …]
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| /linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | mscc,ocelot.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Ocelot Switch Family
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
20 them performs packet I/O primarily through an Ethernet port of the switch
[all …]
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| H A D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
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| H A D | mediatek,mt7628-esw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/mediatek,mt7628-esw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT7628 Embedded Ethernet Switch
10 - Joris Vaisvila <joey@tinyisr.com>
13 The MT7628 SoC's built-in Ethernet Switch has five user ports and one
15 integrated Fast Ethernet PHYs. The switch registers are directly mapped in
19 - $ref: dsa.yaml#/$defs/ethernet-ports
23 const: mediatek,mt7628-esw
[all …]
|
| H A D | qca8k.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros QCA83xx switch family
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
[all …]
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| H A D | qca,ar9331.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR9331 built-in switch
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 Qualcomm Atheros AR9331 is a switch built-in to Atheros AR9331 WiSoC and
14 addressable over internal MDIO bus. All PHYs are built-in as well.
18 const: qca,ar9331-switch
26 interrupt-controller: true
28 '#interrupt-cells':
[all …]
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | microchip,sparx5-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Ethernet switch controller
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
12 - Daniel Machon <daniel.machon@microchip.com>
15 The SparX-5 Enterprise Ethernet switch family provides a rich set of
16 Enterprise switching features such as advanced TCAM-based VLAN and
[all …]
|
| H A D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
[all …]
|
| H A D | microchip,lan966x-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Lan966x Ethernet switch controller
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
[all …]
|
| H A D | hisilicon-hns-nic.txt | 4 - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
5 "hisilicon,hns-nic-v1" is for hip05.
6 "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
7 - ae-handle: accelerator engine handle for hns,
9 see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
14 The remaining 6 PHYs are taken according to the mode of DSAF.
16 In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The
17 port-id can be 2 to 7. Here is the diagram:
18 +-----+---------------+
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/gpio/ |
| H A D | hw_ddc.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
39 gpio_reg_shift(ddc->shifts->field_name), ddc->masks->field_name
42 ddc->base.base.ctx
44 (ddc->regs->reg)
51 dal_hw_gpio_destruct(&pin->base); in dal_hw_ddc_destruct()
77 hw_gpio = &ddc->base; in set_config()
89 switch (config_data->config.ddc.type) { in set_config()
91 /* On plug-in, there is a transient level on the pad in set_config()
92 * which must be discharged through the internal pull-down. in set_config()
93 * Enable internal pull-down, 2.5msec discharge time in set_config()
[all …]
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-bd9571mwv-regulator | 1 What: /sys/bus/i2c/devices/.../bd9571mwv-regulator.*.auto/backup_mode
5 Description: Read/write the current state of DDR Backup Mode, which controls
10 A. With a momentary power switch (or pulse signal), DDR
11 Backup Mode is enabled by default when available, as the
13 B. With a toggle power switch (or level signal), the
16 1. Configure PMIC for backup mode, to change the role of
17 the accessory power switch from a power switch to a
18 wake-up switch,
19 2. Switch accessory power switch off, to prepare for
23 4. Switch accessory power switch on, to resume the
[all …]
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | atombios_crtc.c | 2 * Copyright 2007-8 Advanced Micro Devices, Inc.
31 #include "atom-bits.h"
39 struct drm_display_mode *mode, in amdgpu_atombios_crtc_overscan_setup() argument
42 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_overscan_setup()
51 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_overscan_setup()
53 switch (amdgpu_crtc->rmx_type) { in amdgpu_atombios_crtc_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
[all …]
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| /linux/sound/soc/codecs/ |
| H A D | max9867.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright 2013-2015 Maxim Integrated Products
6 // Copyright 2018 Ladislav Michl <ladis@linux-mips.org>
42 "Butterworth/8-24"
55 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max9867_adc_dac_event()
71 max9867->adc_dac_active |= BIT(adc_dac); in max9867_adc_dac_event()
73 max9867->adc_dac_active &= ~BIT(adc_dac); in max9867_adc_dac_event()
86 ret = regmap_read(max9867->regma in max9867_filter_get()
103 unsigned int reg, mode = ucontrol->value.enumerated.item[0]; max9867_filter_set() local
[all...] |
| H A D | twl4030.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/mfd/twl4030-audio.h>
64 u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
76 twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte; in tw4030_init_ctl_cache()
86 return -EIO; in twl4030_read()
88 switch (re in twl4030_read()
183 int mode; twl4030_codec_enable() local
1697 u8 mode, old_mode, format, old_format; twl4030_hw_params() local
1928 u8 mode; twl4030_voice_startup() local
1970 u8 old_mode, mode; twl4030_voice_hw_params() local
[all...] |
| /linux/tools/testing/selftests/drivers/net/bonding/ |
| H A D | lag_lib.sh | 2 # SPDX-License-Identifier: GPL-2.0
11 local mode=$2
21 ip link add "$name" up type bond mode "$mode"
36 # Used to test dev->uc handling
38 # Used to test dev->mc handling
49 check_err $? "IPv6 solicited-node multicast mac address not found on a slave"
58 check_err $? "IPv6 solicited-nod
[all...] |
| /linux/drivers/mfd/ |
| H A D | ucb1x00-ts.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Touchscreen driver for UCB1x00-based touchscreens
8 * 21-Jan-2002 <jco@ict.es> :
10 * Added support for synchronous A/D mode. This mode is useful to
34 #include <asm/mach-types.h>
56 struct input_dev *idev = ts->idev; in ucb1x00_ts_evt_add()
67 struct input_dev *idev = ts->idev; in ucb1x00_ts_event_release()
75 * Switch to interrupt mode.
79 ucb1x00_reg_write(ts->ucb, UCB_TS_CR, in ucb1x00_ts_mode_int()
86 * Switch to pressure mode, and read pressure. We don't need to wait
[all …]
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | qcom,wcd939x-usbss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,wcd939x-usbss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm WCD9380/WCD9385 USB SubSystem Altmode/Analog Audio Switch
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 Qualcomm WCD9390/WCD9395 is a standalone Hi-Fi audio codec IC with a
14 functionally separate USB SubSystem for Altmode/Analog Audio Switch
17 USB-C Mux subsystems are external to the IC, thus requiring DT port-endpoint
18 graph description to handle USB-C altmode & orientation switching for Audio
[all …]
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| H A D | dwc2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
22 - const: ingenic,jz4780-otg
[all …]
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| /linux/Documentation/sound/cards/ |
| H A D | cmipci.rst | 2 Brief Notes on C-Media 8338/8738/8768/8770 Driver
8 Front/Rear Multi-channel Playback
9 ---------------------------------
13 DACs, both streams are handled independently unlike the 4/6ch multi-
22 - The first DAC supports U8 and S16LE formats, while the second DAC
24 - The second DAC supports only two channel stereo.
30 The rear output can be heard only when "Four Channel Mode" switch is
35 When "Four Channel Mode" switch is off, the output from rear speakers
38 before your turn off this switch.
44 on and "double DAC" mode. Actually I could hear separate 4 channels
[all …]
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| /linux/arch/arm/mach-tegra/ |
| H A D | pm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
29 #include <asm/proc-fns.h>
50 switch (tegra_get_chip_id()) { in tegra_tear_down_cpu_init()
141 if (tegra_cpu_car_ops->rail_off_ready && in tegra_sleep_cpu()
143 return -EBUSY; in tegra_sleep_cpu()
148 * MMU-on if cache maintenance is done via Trusted Foundations in tegra_sleep_cpu()
150 * if any of secondary CPU's is online and this is the LP2-idle in tegra_sleep_cpu()
151 * code-path only for Tegra20/30. in tegra_sleep_cpu()
162 * 2) Disable D-cache. This need to be taken into account in in tegra_sleep_cpu()
[all …]
|