Lines Matching +full:mode +full:- +full:switch

1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * QE UCC API Set - UCC specific routines implementations.
33 	if (ucc_num > UCC_MAX_NUM - 1)
34 		return -EINVAL;
37 	qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
50  * 'ucc_num' is the UCC number, from 0 - 7.
61 	switch (ucc_num) {
62 	case 0: guemr = &qe_immr->ucc1.slow.guemr;
64 	case 1: guemr = &qe_immr->ucc2.slow.guemr;
66 	case 2: guemr = &qe_immr->ucc3.slow.guemr;
68 	case 3: guemr = &qe_immr->ucc4.slow.guemr;
70 	case 4: guemr = &qe_immr->ucc5.slow.guemr;
72 	case 5: guemr = &qe_immr->ucc6.slow.guemr;
74 	case 6: guemr = &qe_immr->ucc7.slow.guemr;
76 	case 7: guemr = &qe_immr->ucc8.slow.guemr;
79 		return -EINVAL;
94 	*cmxucr = &qe_immr->qmx.cmxucr[cmx];
95 	*shift = 16 - 8 * (ucc_num & 2);
105 	if (ucc_num > UCC_MAX_NUM - 1)
106 		return -EINVAL;
120 	enum comm_dir mode)
128 	if (ucc_num > UCC_MAX_NUM - 1)
129 		return -EINVAL;
132 	if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))
133 		return -EINVAL;
137 	switch (reg_num) {
139 		switch (clock) {
154 		switch (clock) {
169 		switch (clock) {
185 		switch (clock) {
205 		return -ENOENT;
207 	if (mode == COMM_DIR_RX)
218 	int clock_bits = -EINVAL;
226 	switch (tdm_num) {
231 		switch (clock) {
252 		switch (clock) {
278 	int clock_bits = -EINVAL;
280 	switch (tdm_num) {
282 		switch (clock) {
294 		switch (clock) {
306 		switch (clock) {
318 		switch (clock) {
330 		switch (clock) {
342 		switch (clock) {
354 		switch (clock) {
366 		switch (clock) {
384 	int clock_bits = -EINVAL;
386 	switch (tdm_num) {
388 		switch (clock) {
400 		switch (clock) {
412 		switch (clock) {
424 		switch (clock) {
436 		switch (clock) {
448 		switch (clock) {
460 		switch (clock) {
472 		switch (clock) {
488 /* tdm_num: TDM A-H port num is 0-7 */
489 static int ucc_get_tdm_rxtx_clk(enum comm_dir mode, u32 tdm_num,
497 	if (mode == COMM_DIR_RX)
499 	if (mode == COMM_DIR_TX)
504 static u32 ucc_get_tdm_clk_shift(enum comm_dir mode, u32 tdm_num)
508 	shift = (mode == COMM_DIR_RX) ? RX_CLK_SHIFT_BASE : TX_CLK_SHIFT_BASE;
510 		shift -= tdm_num * 4;
512 		shift -= (tdm_num - 4) * 4;
518 			 enum comm_dir mode)
525 	qe_mux_reg = &qe_immr->qmx;
528 		return -EINVAL;
531 	if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)
532 		return -EINVAL;
534 	clock_bits = ucc_get_tdm_rxtx_clk(mode, tdm_num, clock);
536 		return -EINVAL;
538 	shift = ucc_get_tdm_clk_shift(mode, tdm_num);
540 	cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l :
541 				  &qe_mux_reg->cmxsi1cr_h;
550 				   enum comm_dir mode)
552 	int source = -EINVAL;
554 	if (mode == COMM_DIR_RX && clock == QE_RSYNC_PIN) {
558 	if (mode == COMM_DIR_TX && clock == QE_TSYNC_PIN) {
563 	switch (tdm_num) {
566 		switch (clock) {
579 		switch (clock) {
592 		switch (clock) {
605 		switch (clock) {
621 static u32 ucc_get_tdm_sync_shift(enum comm_dir mode, u32 tdm_num)
625 	shift = (mode == COMM_DIR_RX) ? RX_SYNC_SHIFT_BASE : TX_SYNC_SHIFT_BASE;
626 	shift -= tdm_num * 2;
632 			  enum comm_dir mode)
638 	qe_mux_reg = &qe_immr->qmx;
641 		return -EINVAL;
644 	if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)
645 		return -EINVAL;
647 	source = ucc_get_tdm_sync_source(tdm_num, clock, mode);
649 		return -EINVAL;
651 	shift = ucc_get_tdm_sync_shift(mode, tdm_num);
653 	qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr,