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Searched +full:mmp2 +full:- +full:audio (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dmarvell,mmp2-audio-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,mmp2-audio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP2 Audio Clock Controller
10 - Lubomir Rintel <lkundrak@v3.sk>
13 The audio clock controller generates and supplies the clocks to the audio
20 <dt-bindings/clock/marvell,mmp2-audio.h>.
25 - marvell,mmp2-audio-clock
32 - description: Audio subsystem clock
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/linux/arch/arm/boot/dts/marvell/
H A Dmmp2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
9 #include <dt-bindings/clock/marvell,mmp2-audio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
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/linux/drivers/clk/mmp/
H A Dclk-audio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MMP Audio Clock Controller driver
8 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/marvell,mmp2-audio.h>
17 /* Audio Controller Registers */
22 /* SSPA Audio Control Register */
33 /* SSPA Audio PLL Control 0 Register */
50 /* SSPA Audio PLL Control 1 Register */
125 aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_recalc_rate()
133 aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_recalc_rate()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
8 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
10 obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
11 obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o
12 obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o
14 obj-$(CONFIG_COMMON_CLK_PXA1908) += clk-pxa1908-apbc.o clk-pxa1908-apbcp.o \
15 clk-pxa1908-mpmu.o clk-pxa1908-apmu.o
17 obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o
H A Dclk-of-mmp2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mmp2 clock framework source file
19 #include <dt-bindings/clock/marvell,mmp2.h>
20 #include <dt-bindings/power/marvell,mmp2.h>
182 struct mmp_clk_unit *unit = &pxa_unit->unit; in mmp2_main_clk_init()
187 if (pxa_unit->model == CLK_MODEL_MMP3) { in mmp2_main_clk_init()
189 pxa_unit->mpmu_base, in mmp2_main_clk_init()
193 pxa_unit->mpmu_base, in mmp2_main_clk_init()
202 pxa_unit->mpmu_base + MPMU_UART_PLL, in mmp2_main_clk_init()
209 pxa_unit->mpmu_base + MPMU_I2S0_PLL, in mmp2_main_clk_init()
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/linux/Documentation/devicetree/bindings/sound/
H A Dmarvell,mmp-sspa.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/marvell,mmp-sspa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvel SSPA Digital Audio Interface
10 - Lubomir Rintel <lkundrak@v3.sk>
13 - $ref: dai-common.yaml#
17 pattern: "^audio-controller(@.*)?$"
20 const: marvell,mmp-sspa
24 - description: RX block
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/linux/drivers/clk/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
67 generators of audio clocks.
80 This driver supports Maxim 9485 Programmable Audio Clock Generator
87 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
91 tristate "Raspberry Pi RP1-based clock support"
96 This multi-function device has 3 main PLLs and several clock
97 generators to drive the internal sub-peripherals.
106 multi-function device has one fixed-rate oscillator, clocked
137 be pre-programmed to support other configurations and features not yet
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