| /linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | datasource.json | 5 "BriefDescription": "Load finished without experiencing an L1 miss."
15 …cessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss."
20 … "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss."
30 …he processor's data cache was reloaded from local, remote, or distant memory due to a demand miss."
60 …n": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss."
65 …ption": "The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss."
70 …s instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload."
75 …sor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload."
80 …or's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss."
85 …cessor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss."
[all …]
|
| H A D | memory.json | 5 …t), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is…
10 …"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event co…
15 …"BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event cou…
20 …"BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was us…
25 "BriefDescription": "Cycles in which an L3 miss was pending for this thread."
40 …t), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is…
45 …"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event c…
50 …"BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event coun…
55 …"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation. Whe…
60 …"BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this ev…
[all …]
|
| H A D | marked.json | 15 …t), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is…
20 …"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specif…
25 …"BriefDescription": "Marked Data TLB reload (after a miss) page size 1G. Implies radix translation…
45 "BriefDescription": "Marked instruction suffered an instruction cache miss."
95 …t), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is…
100 …"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specif…
120 …"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When…
125 …a cache was reloaded from local, remote, or distant memory due to a demand miss for a marked load."
130 "BriefDescription": "Marked demand data load miss counted at finish time."
135 …ed from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked load."
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/goldmont/ |
| H A D | cache.json | 20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
24 …anding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unab…
40 "EventName": "LONGEST_LAT_CACHE.MISS",
41 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
61 …e speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the …
94 "PublicDescription": "Counts load uops retired that miss the L1 data cache.",
116 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
228 "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache.",
234 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_O…
239 …"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | cache.json | 20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
24 …anding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unab…
40 "EventName": "LONGEST_LAT_CACHE.MISS",
41 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
61 …e speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the …
94 "PublicDescription": "Counts load uops retired that miss the L1 data cache.",
116 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
239 …"BriefDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in t…
245 …"PublicDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in …
250 …escription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss i…
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| H A D | ifu.json | 3 "PublicDescription": "I-Cache miss on an access from the prefetch block",
6 "BriefDescription": "I-Cache miss on an access from the prefetch block"
9 …ription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l ITLB miss",
12 …cription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l ITLB miss"
51 "PublicDescription": "Micro-predictor miss",
54 "BriefDescription": "Micro-predictor miss"
57 "PublicDescription": "Thread flushed due to TLB miss",
60 "BriefDescription": "Thread flushed due to TLB miss"
63 "PublicDescription": "Thread flushed due to reasons other than TLB miss",
66 "BriefDescription": "Thread flushed due to reasons other than TLB miss"
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | cache.json | 11 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
15 …miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide …
31 "EventName": "LONGEST_LAT_CACHE.MISS",
78 …"PublicDescription": "This event counts the number of load ops retired that miss in L1 Data cache.…
98 … "PublicDescription": "This event counts the number of load ops retired that miss in the L2.",
107 "PublicDescription": "This event counts the number of load ops retired that had UTLB miss.",
131 "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2.",
151 …"BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibl…
161 …efDescription": "Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response…
181 "BriefDescription": "Counts any data read (demand & prefetch) that miss L2.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | memory.json | 3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
12 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
204 "BriefDescription": "Demand Data Read requests who miss L3 cache",
208 "PublicDescription": "Demand Data Read requests who miss L3 cache.",
213 …"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the sup…
222 …on": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the sup…
230 …"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the su…
239 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.",
249 …"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified dat…
259 …"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared …
[all …]
|
| /linux/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/ |
| H A D | common.json | 10 "BriefDescription": "miss MMU STLB"
20 "BriefDescription": "miss MMU PTE-Cache"
30 "BriefDescription": "BTB prediction miss"
35 "BriefDescription": "ITLB miss"
45 "BriefDescription": "ICache miss"
55 "BriefDescription": "condition branch instruction miss"
65 "BriefDescription": "return instruction miss"
70 "BriefDescription": "indirect JR instruction miss (inlcude without target)"
120 "BriefDescription": "miss DTLB"
130 "BriefDescription": "load instruction miss DCache"
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | memory.json | 134 "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC",
144 …"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data retur…
154 …"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data forwa…
184 …"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the…
194 …"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the dat…
204 …"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the…
214 "BriefDescription": "Counts all demand code reads that miss the LLC",
224 …"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from lo…
234 …"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from re…
244 …"BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state …
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/westmereex/ |
| H A D | virtual-memory.json | 11 "BriefDescription": "DTLB load miss large page walks",
19 "BriefDescription": "DTLB load miss caused by low part of address",
35 "BriefDescription": "DTLB load miss page walks complete",
43 "BriefDescription": "DTLB load miss page walk cycles",
59 "BriefDescription": "DTLB miss large page walks",
83 "BriefDescription": "DTLB miss page walks",
91 "BriefDescription": "DTLB miss page walk cycles",
115 "BriefDescription": "ITLB miss",
123 "BriefDescription": "ITLB miss large page walks",
131 "BriefDescription": "ITLB miss page walks",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/westmereep-dp/ |
| H A D | virtual-memory.json | 11 "BriefDescription": "DTLB load miss large page walks",
19 "BriefDescription": "DTLB load miss caused by low part of address",
35 "BriefDescription": "DTLB load miss page walks complete",
43 "BriefDescription": "DTLB load miss page walk cycles",
59 "BriefDescription": "DTLB miss large page walks",
83 "BriefDescription": "DTLB miss page walks",
91 "BriefDescription": "DTLB miss page walk cycles",
115 "BriefDescription": "ITLB miss",
123 "BriefDescription": "ITLB miss large page walks",
131 "BriefDescription": "ITLB miss page walks",
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | pipeline.json | 9 …ed due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is …
12 …ed due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is …
15 …ued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is a…
18 …ued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is a…
57 …"PublicDescription": "No operation issued due to the backend, load, cache miss.This event counts e…
60 …"BriefDescription": "No operation issued due to the backend, load, cache miss.This event counts ev…
63 …"PublicDescription": "No operation issued due to the backend, load, TLB miss.This event counts eve…
66 …"BriefDescription": "No operation issued due to the backend, load, TLB miss.This event counts ever…
75 …"PublicDescription": "No operation issued due to the backend, store, TLB miss.This event counts ev…
78 …"BriefDescription": "No operation issued due to the backend, store, TLB miss.This event counts eve…
|
| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | uncore-cache.json | 185 …"BriefDescription": "Cache Lookups: Read Requests, Read Prefetches, and Snoops which miss the Cach…
717 "BriefDescription": "UNC_CHA_REMOTE_SF.MISS",
720 "EventName": "UNC_CHA_REMOTE_SF.MISS",
948 "BriefDescription": "CLFlush transactions from a CXL device which miss the L3.",
958 "BriefDescription": "FsRdCur transactions from a CXL device which miss the L3.",
968 "BriefDescription": "FsRdCurPtl transactions from a CXL device which miss the L3.",
978 "BriefDescription": "ItoM transactions from a CXL device which miss the L3.",
988 "BriefDescription": "ItoMWr transactions from a CXL device which miss the L3.",
998 "BriefDescription": "MemPushWr transactions from a CXL device which miss the L3.",
1008 "BriefDescription": "WCiL transactions from a CXL device which miss the L3.",
[all …]
|
| H A D | virtual-memory.json | 3 "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
7 …"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TL…
17 …"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page …
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
62 …s the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle…
67 "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
71 …"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)…
81 …"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page …
126 …"Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle…
131 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | virtual-memory.json | 21 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not …
30 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
34 …"PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB le…
39 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
43 …"PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB le…
48 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
57 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
65 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
74 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
87 …"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | virtual-memory.json | 21 …"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not …
30 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
34 …"PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB le…
39 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
43 …"PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB le…
48 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
57 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
65 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
74 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
87 …"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page…
[all …]
|
| /linux/tools/perf/pmu-events/arch/powerpc/power9/ |
| H A D | metrics.json | 74 "BriefDescription": "Completion stall by Dcache miss which resolved off node memory/cache",
80 …"BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L…
86 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl…
92 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 without conf…
98 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
104 "BriefDescription": "Completion stall due to cache miss resolving missed the L3",
110 "BriefDescription": "Completion stall due to cache miss that resolves in local memory",
116 … "BriefDescription": "Completion stall by Dcache miss which resolved outside of local memory",
122 …"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or mem…
152 …n": "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was ful…
[all …]
|
| /linux/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/ |
| H A D | cache.json | 10 "BriefDescription": "L1 instruction cache miss"
15 "BriefDescription": "I-UTLB miss"
20 "BriefDescription": "D-UTLB miss"
25 "BriefDescription": "JTLB miss"
35 "BriefDescription": "L1 data cache read miss"
45 "BriefDescription": "L1 data cache write miss"
55 "BriefDescription": "LL Cache read miss"
65 "BriefDescription": "LL Cache write miss"
|
| /linux/tools/perf/pmu-events/arch/x86/westmereep-sp/ |
| H A D | virtual-memory.json | 11 "BriefDescription": "DTLB load miss caused by low part of address",
27 "BriefDescription": "DTLB load miss page walks complete",
35 "BriefDescription": "DTLB load miss page walk cycles",
51 "BriefDescription": "DTLB miss large page walks",
67 "BriefDescription": "DTLB miss page walks",
75 "BriefDescription": "DTLB miss page walk cycles",
99 "BriefDescription": "ITLB miss",
107 "BriefDescription": "ITLB miss page walks",
115 "BriefDescription": "ITLB miss page walk cycles",
132 "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | uncore-cache.json | 185 …"BriefDescription": "Cache Lookups: Read Requests, Read Prefetches, and Snoops which miss the Cach…
717 "BriefDescription": "UNC_CHA_REMOTE_SF.MISS",
720 "EventName": "UNC_CHA_REMOTE_SF.MISS",
948 "BriefDescription": "CLFlush transactions from a CXL device which miss the L3.",
958 "BriefDescription": "FsRdCur transactions from a CXL device which miss the L3.",
968 "BriefDescription": "FsRdCurPtl transactions from a CXL device which miss the L3.",
978 "BriefDescription": "ItoM transactions from a CXL device which miss the L3.",
988 "BriefDescription": "ItoMWr transactions from a CXL device which miss the L3.",
998 "BriefDescription": "MemPushWr transactions from a CXL device which miss the L3.",
1008 "BriefDescription": "WCiL transactions from a CXL device which miss the L3.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | pipeline.json | 21 …, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue …
24 …, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue …
27 … the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and…
30 … the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and…
69 …"PublicDescription": "No operation issued due to the backend, load, cache miss. This event counts …
72 …"BriefDescription": "No operation issued due to the backend, load, cache miss. This event counts e…
75 …"PublicDescription": "No operation issued due to the backend, load, TLB miss. This event counts ev…
78 …"BriefDescription": "No operation issued due to the backend, load, TLB miss. This event counts eve…
87 …"PublicDescription": "No operation issued due to the backend, store, TLB miss. This event counts e…
90 …"BriefDescription": "No operation issued due to the backend, store, TLB miss. This event counts ev…
|
| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
7 …"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TL…
17 …"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page …
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
53 …s the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle…
58 "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
62 …"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)…
72 …"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page …
108 …"Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle…
113 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
7 …"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TL…
17 …"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page …
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
62 …s the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle…
67 "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
71 …"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)…
81 …"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page …
126 …"Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle…
131 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
7 …"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TL…
17 …"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page …
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
62 …s the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle…
67 "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
71 …"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)…
81 …"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page …
126 …"Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle…
131 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
[all …]
|