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Searched +full:mips +full:- +full:cm (Results 1 – 14 of 14) sorted by relevance

/linux/arch/mips/include/asm/
H A Dpm-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
11 * The CM & CPC can only handle coherence & power control on a per-core basis,
13 * enter or exit states requiring CM or CPC assistance in unison.
25 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
32 * cps_pm_support_state - determine whether the system supports a PM state
40 * cps_pm_enter_state - enter a PM state
43 * Enter the given PM state. If coupled_coherence is non-zero then it is
45 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
H A Dmips-cpc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-cpc.h
21 * mips_cpc_default_phys_base - retrieve the default physical base address of
26 * implemented per-platform.
31 * mips_cpc_probe - probe for a Cluster Power Controller
34 * a CPC is successfully detected, else -errno.
41 return -ENODEV; in mips_cpc_probe()
46 * mips_cpc_present - determine whether a Cluster Power Controller is present
80 /* CPC_ACCESS - Control core/IOCU access to CPC registers prior to CM 3 */
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H A Daddrspace.h35 * 32-bit MIPS address spaces
66 * The compatibility segments use the full 64-bit sign extended value. Note
67 * the R8000 doesn't have them so don't reference these in generic MIPS code.
100 * These are the traditional names used in the 32-bit universe.
129 * 64-bit address conversions
134 #define PHYS_TO_XKPHYS(cm, a) (XKPHYS | (_ACAST64_(cm) << 59) | (a)) argument
137 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
139 * R8000 implements most with its 48-bit physical address space.
141 #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
144 #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
/linux/arch/mips/kernel/
H A Dmips-cpc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
14 #include <asm/mips-cps.h>
28 cpc_node = of_find_compatible_node(of_root, NULL, "mti,mips-cpc"); in mips_cpc_default_phys_base()
40 * mips_cpc_phys_base - retrieve the physical base address of the CPC
81 return -ENODEV; in mips_cpc_probe()
85 return -ENXIO; in mips_cpc_probe()
95 /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */ in mips_cpc_lock_other()
105 * Ensure the core-other region reflects the appropriate core & in mips_cpc_lock_other()
116 /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */ in mips_cpc_unlock_other()
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the Linux/MIPS kernel.
6 always-$(KBUILD_BUILTIN) := vmlinux.lds
8 obj-y += head.o branch.o cmpxchg.o elf.o entry.o genex.o idle.o irq.o \
14 obj-y += cpu-r3k-probe.o
16 obj-y += cpu-probe.o
26 obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
27 obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
28 obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
29 obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
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H A Dsmp-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
19 #include <asm/mips-cps.h>
22 #include <asm/pm-cps.h>
26 #include <asm/smp-cps.h>
59 /* Set endianness & power up the CM */ in power_up_other_cluster()
65 /* Wait for the CM to start up */ in power_up_other_cluster()
78 timeout--; in power_up_other_cluster()
80 pr_warn("Waiting for cluster %u CM to power up... STAT_CONF=0x%x\n", in power_up_other_cluster()
159 0x0, CSEGX_SIZE - 1); in allocate_cps_vecs()
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/linux/arch/mips/bmips/
H A Dsetup.c24 #include <asm/cpu-type.h>
27 #include <asm/smp-ops.h>
40 * with "brcm,bmips-cbr-reg" in the "cpus" node.
63 * Some experimental CM boxes are set up to let CM own the Viper TP0 in bcm3384_viper_quirks()
65 * load address to a non-conflicting region (e.g. via in bcm3384_viper_quirks()
67 * If we detect this condition, we need to move the MIPS exception in bcm3384_viper_quirks()
71 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our in bcm3384_viper_quirks()
131 { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
132 { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
174 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0) in plat_time_init()
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/linux/arch/mips/mti-malta/
H A Dmalta-dtshim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
15 #include <asm/mips-boards/generic.h>
16 #include <asm/mips-boards/malta.h>
17 #include <asm/mips-cps.h>
91 size -= size_preio; in gen_fdt_mem_array()
99 * obscures 256MB from 0x10000000-0x1fffffff. in gen_fdt_mem_array()
105 size -= SZ_256M; in gen_fdt_mem_array()
115 * obscures 256MB from 0x10000000-0x1fffffff in the low alias in gen_fdt_mem_array()
169 * SOC-it swaps, or perhaps doesn't swap, when DMA'ing in append_memory()
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/linux/arch/mips/ralink/
H A Dmt7621.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <asm/smp-ops.h>
19 #include <asm/mips-cps.h>
20 #include <asm/mach-ralink/ralink_regs.h>
21 #include <asm/mach-ralink/mt7621.h>
35 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); in pcibios_root_bridge_prepare()
38 return -EINVAL; in pcibios_root_bridge_prepare()
46 mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK; in pcibios_root_bridge_prepare()
47 WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask); in pcibios_root_bridge_prepare()
49 write_gcr_reg1_base(entry->res->start); in pcibios_root_bridge_prepare()
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/linux/drivers/irqchip/
H A Dirq-mips-gic.c6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
26 #include <asm/mips-cps.h>
30 #include <dt-bindings/interrupt-controller/mips-gic.h>
44 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
47 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
98 * for_each_online_cpu_gic() - Iterate over online CPUs, access local registers
109 for ((cpu) = __gic_with_next_online_cpu(-1); \
115 * gic_irq_lock_cluster() - Lock redirect block access to IRQ's cluster
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/linux/drivers/misc/
H A Dpch_phub.c1 // SPDX-License-Identifier: GPL-2.0-only
47 /* CM-iTC */
58 #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
59 #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
65 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
86 * struct pch_phub_reg - PHUB register structure
137 * pch_phub_read_modify_write_reg() - Reading modifying and writing register
147 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset; in pch_phub_read_modify_write_reg()
151 /* pch_phub_save_reg_conf - saves register configuration */
157 void __iomem *p = chip->pch_phub_base_address; in pch_phub_save_reg_conf()
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/linux/arch/mips/mm/
H A Dc-r4k.c22 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
29 #include <asm/cpu-features.h>
30 #include <asm/cpu-type.h>
38 #include <asm/mips-cps.h>
43 * R4K_HIT - Virtual user or kernel address based cache operations. The
46 * R4K_INDEX - Index based cache operations.
53 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
68 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ in r4k_op_needs_ipi()
74 * be needed, but only if there are foreign CPUs (non-siblings with in r4k_op_needs_ipi()
388 * is not cached in the S-cache, we know it also won't be in local_r4k___flush_cache_all()
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/linux/lib/crypto/riscv/
H A Dpoly1305-riscv.pl2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
5 # Written by Andy Polyakov, @dot-asm, initially for use with OpenSSL.
8 # Poly1305 hash for RISC-V.
12 # In the essence it's pretty straightforward transliteration of MIPS
13 # module [without big-endian option].
15 # 1.8 cycles per byte on U74, >100% faster than compiler-generated
34 for (@ARGV) { $output=$_ if (/\w[\w\-]*\.\w+$/); }
51 # 64-bit code path...
86 andi $inp,$inp,-8 # align $inp
107 addi $tmp0,$tmp0,-63 # 0x00000000ffffffc1
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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