micro\-TLB (full) in projects: linux - OpenGrok search results

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Searched +full:micro +full:- +full:tlb (Results 1 – 25 of 103) sorted by relevance

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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A D	ifu.json	3 "PublicDescription": "I-Cache miss on an access from the prefetch block", 6 "BriefDescription": "I-Cache miss on an access from the prefetch block" 9 …"PublicDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l… 12 …"BriefDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l … 15 …"PublicDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 p… 18 …"BriefDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 pr… 21 … "PublicDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor", 24 "BriefDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor" 27 "PublicDescription": "Micro-predictor hit with immediate redirect", 30 "BriefDescription": "Micro-predictor hit with immediate redirect" [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A D	cache.json	111 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM", 114 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM" 117 "PublicDescription": "Number of ways read in the instruction cache - Data RAM", 120 "BriefDescription": "Number of ways read in the instruction cache - Data RAM" 129 "PublicDescription": "Level 1 PLD TLB refill", 132 "BriefDescription": "Level 1 PLD TLB refill" 135 …"PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwa… 138 …"BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwar… 141 "PublicDescription": "Level 1 TLB flush", 144 "BriefDescription": "Level 1 TLB flush" [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A D	metrics.json	12 "BriefDescription": "Core-to-uncore bus utilization", 89 "BriefDescription": "Giga-floating point operations per second", 156 … "BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)", 162 "MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))", 163 "BriefDescription": "Of all the micro-operations issued, what proportion are lost", 169 "MetricExpr": "1 - OP_RETIRED / OP_SPEC", 170 …"BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed… 191 …"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss… 205 …escription": "Proportion of cycles stalled and no operations delivered from frontend and TLB miss", 212 …s the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication o… [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A D	metrics.json	12 "BriefDescription": "Core-to-uncore bus utilization", 89 "BriefDescription": "Giga-floating point operations per second", 156 … "BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)", 162 "MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))", 163 "BriefDescription": "Of all the micro-operations issued, what proportion are lost", 169 "MetricExpr": "1 - OP_RETIRED / OP_SPEC", 170 …"BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed… 191 …BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss", 205 …escription": "Proportion of cycles stalled and no operations delivered from frontend and TLB miss", 212 …s the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication o… [all …]
/linux/arch/powerpc/platforms/8xx/
H A D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0 33 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)" 39 MPC885 Evaluation System and/or the CWH-PPC-885XN-VE. 42 bool "Analogue & Micro Adder 875" 45 This enables support for the Analogue & Micro Adder 875 56 menu "Freescale Ethernet driver platform-specific options" 76 Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2 77 (often 2-nd UART) will not work if this is enabled. 83 Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1 84 (often 1-nd UART) will not work if this is enabled. [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
H A D	pipeline.json	10 … DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre… 20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p… 25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed" 30 …"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instruc… 40 … "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
/linux/tools/perf/pmu-events/arch/arm64/
H A D	common-and-microarch.json	15 "PublicDescription": "Attributable Level 1 instruction TLB refill", 18 "BriefDescription": "Attributable Level 1 instruction TLB refill" 33 "PublicDescription": "Attributable Level 1 data TLB refill", 36 "BriefDescription": "Attributable Level 1 data TLB refill" 129 "PublicDescription": "Attributable Level 1 data cache write-back", 132 "BriefDescription": "Attributable Level 1 data cache write-back" 147 "PublicDescription": "Attributable Level 2 data cache write-back", 150 "BriefDescription": "Attributable Level 2 data cache write-back" 219 "PublicDescription": "Attributable Level 1 data or unified TLB access", 222 "BriefDescription": "Attributable Level 1 data or unified TLB access" [all …]
/linux/Documentation/devicetree/bindings/iommu/
H A D	renesas,ipmmu-vmsa.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas VMSA-Compatible IOMMU 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 15 connected to the IPMMU through a port called micro-TLB. 20 - items: 21 - enum: 22 - renesas,ipmmu-r8a73a4 # R-Mobile APE6 [all …]`
H A D	qcom,apq8064-iommu.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - David Heidelberg <david@ixit.cz> 16 outside of the CPU, each connected to the IOMMU through a port called micro-TLB. 20 const: qcom,apq8064-iommu 24 - description: interface clock for register accesses 25 - description: functional clock for bus accesses 27 clock-names: [all …]`
/linux/tools/perf/Documentation/
H A D	perf-arm-spe.txt	`1 perf-arm-spe(1) 5 ---- 6 perf-arm-spe - Support for Arm Statistical Profiling Extension within Perf tools 9 -------- 11 'perf record' -e arm_spe// 14 ----------- 17 events down to individual instructions. Rather than being interrupt-driven, it picks an 33 architectural instructions or all micro-ops. Sampling happens at a programmable interval. The 35 sample. This minimum interval is used by the driver if no interval is specified. A pseudo-random 62 ---------------- [all …]`
H A D	perf-amd-ibs.txt	`1 perf-amd-ibs(1) 5 ---- 6 perf-amd-ibs - Support for AMD Instruction-Based Sampling (IBS) with perf tool 9 -------- 11 'perf record' -e ibs_op// 12 'perf record' -e ibs_fetch// 15 ----------- 17 Instruction-Based Sampling (IBS) provides precise Instruction Pointer (IP) 20 execution (micro-op execution to be precise) with details like d-cache 21 hit/miss, d-TLB hit/miss, cache miss latency, load/store data source, branch [all …]`
/linux/drivers/gpu/drm/xe/
H A D	xe_exec_queue_types.h	1 /* SPDX-License-Identifier: MIT / 25 XE_EXEC_QUEUE_PRIORITY_UNSET = -2, / For execlist usage only / 35 struct xe_exec_queue - Execution queue 66 /** @msix_vec: MSI-X vector (for platforms that support it) / 72 @last_fence: last fence on exec queue, protected by vm->lock in write 73 * mode if bind exec queue, protected by dma resv lock if non-bind exec 84 /* child of VM queue for multi-tile VM jobs / 100 /* @multi_gt_list: list head for VM bind engines if multi-GT / 102 /* @multi_gt_link: link for VM bind engines if multi-GT / 115 /* @sched_props.timeslice_us: timeslice period in micro-seconds */ [all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	jkt-metrics.json	4 "MetricExpr": "cstate_pkg@c2\\-residency@ / msr@tsc@", 11 "MetricExpr": "cstate_core@c3\\-residency@ / msr@tsc@", 18 "MetricExpr": "cstate_pkg@c3\\-residency@ / msr@tsc@", 25 "MetricExpr": "cstate_core@c6\\-residency@ / msr@tsc@", 32 "MetricExpr": "cstate_pkg@c6\\-residency@ / msr@tsc@", 39 "MetricExpr": "cstate_core@c7\\-residency@ / msr@tsc@", 46 "MetricExpr": "cstate_pkg@c7\\-residency@ / msr@tsc@", 59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", 74 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", 79 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete… [all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A D	snb-metrics.json	4 "MetricExpr": "cstate_pkg@c2\\-residency@ / msr@tsc@", 11 "MetricExpr": "cstate_core@c3\\-residency@ / msr@tsc@", 18 "MetricExpr": "cstate_pkg@c3\\-residency@ / msr@tsc@", 25 "MetricExpr": "cstate_core@c6\\-residency@ / msr@tsc@", 32 "MetricExpr": "cstate_pkg@c6\\-residency@ / msr@tsc@", 39 "MetricExpr": "cstate_core@c7\\-residency@ / msr@tsc@", 46 "MetricExpr": "cstate_pkg@c7\\-residency@ / msr@tsc@", 59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", 74 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", 79 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete… [all …]
/linux/arch/mips/mm/
H A D	tlb-funcs.S	`6 * Micro-assembler generated tlb handler functions. 10 * Based on mm/page-funcs.c 12 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>`
/linux/arch/arc/mm/
H A D	tlbex.S	1 /* SPDX-License-Identifier: GPL-2.0-only / 3 TLB Exception Handling for ARC 5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 8 * -MMU v1: moved out legacy code into a separate file 9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore, 13 * -For MMU V2, we need not do heuristics at the time of committing a D-TLB 14 * entry, so that it doesn't knock out its I-TLB entry 15 * -Some more fine tuning: 19 * -Practically rewrote the I/D TLB Miss handlers 26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A D	recommended.json	`4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", 119 "MetricGroup": "tlb" 148 "BriefDescription": "Micro-ops Dispatched", 160 "BriefDescription": "Micro-ops Retired" 168 "ScaleUnit": "3e-5MiB" 177 "ScaleUnit": "6.1e-5MiB"`
/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A D	recommended.json	`4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", 119 "MetricGroup": "tlb" 148 "BriefDescription": "Micro-ops Dispatched", 160 "BriefDescription": "Micro-ops Retired" 168 "ScaleUnit": "3e-5MiB" 177 "ScaleUnit": "6.1e-5MiB"`
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A D	virtual-memory.json	21 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de… 34 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 55 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 61 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 65 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 75 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 85 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 95 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 105 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 115 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	hsx-metrics.json	4 "MetricExpr": "cstate_pkg@c2\\-residency@ / msr@tsc@", 11 "MetricExpr": "cstate_core@c3\\-residency@ / msr@tsc@", 18 "MetricExpr": "cstate_pkg@c3\\-residency@ / msr@tsc@", 25 "MetricExpr": "cstate_core@c6\\-residency@ / msr@tsc@", 32 "MetricExpr": "cstate_pkg@c6\\-residency@ / msr@tsc@", 39 "MetricExpr": "cstate_core@c7\\-residency@ / msr@tsc@", 46 "MetricExpr": "cstate_pkg@c7\\-residency@ / msr@tsc@", 79 …al number of completed instructions. This implies it missed in the DTLB and further levels of TLB", 86 …al number of completed instructions. This implies it missed in the DTLB and further levels of TLB", 105 …mplies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB", [all …]
/linux/arch/arm64/mm/
H A D	contpte.c	1 // SPDX-License-Identifier: GPL-2.0-only 41 unsigned long last_addr = addr + PAGE_SIZE * (nr - 1); in contpte_try_unfold_partial() 42 pte_t last_ptep = ptep + nr - 1; in contpte_try_unfold_partial() 81 - When folding N smaller non-contiguous ptes as 1 contiguous block. in contpte_convert() 82 * - When unfolding a contiguous block into N smaller non-contiguous ptes. in contpte_convert() 86 * 0) Initial page-table layout: in contpte_convert() 88 * +----+----+----+----+ in contpte_convert() 89 * \|RO,n\|RO,n\|RO,n\|RW,n\| <--- last page being set as RO in contpte_convert() 90 * +----+----+----+----+ in contpte_convert() 94 * +----+----+----+----+ in contpte_convert() [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	bdx-metrics.json	4 "MetricExpr": "cstate_pkg@c2\\-residency@ / msr@tsc@", 11 "MetricExpr": "cstate_core@c3\\-residency@ / msr@tsc@", 18 "MetricExpr": "cstate_pkg@c3\\-residency@ / msr@tsc@", 25 "MetricExpr": "cstate_core@c6\\-residency@ / msr@tsc@", 32 "MetricExpr": "cstate_pkg@c6\\-residency@ / msr@tsc@", 39 "MetricExpr": "cstate_core@c7\\-residency@ / msr@tsc@", 46 "MetricExpr": "cstate_pkg@c7\\-residency@ / msr@tsc@", 79 …al number of completed instructions. This implies it missed in the DTLB and further levels of TLB", 86 …al number of completed instructions. This implies it missed in the DTLB and further levels of TLB", 105 …mplies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB", [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	hsw-metrics.json	4 "MetricExpr": "cstate_pkg@c2\\-residency@ / msr@tsc@", 11 "MetricExpr": "cstate_core@c3\\-residency@ / msr@tsc@", 18 "MetricExpr": "cstate_pkg@c3\\-residency@ / msr@tsc@", 25 "MetricExpr": "cstate_core@c6\\-residency@ / msr@tsc@", 32 "MetricExpr": "cstate_pkg@c6\\-residency@ / msr@tsc@", 39 "MetricExpr": "cstate_core@c7\\-residency@ / msr@tsc@", 46 "MetricExpr": "cstate_pkg@c7\\-residency@ / msr@tsc@", 59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", 78 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde… 95 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh… [all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	ivb-metrics.json	4 "MetricExpr": "cstate_pkg@c2\\-residency@ / msr@tsc@", 11 "MetricExpr": "cstate_core@c3\\-residency@ / msr@tsc@", 18 "MetricExpr": "cstate_pkg@c3\\-residency@ / msr@tsc@", 25 "MetricExpr": "cstate_core@c6\\-residency@ / msr@tsc@", 32 "MetricExpr": "cstate_pkg@c6\\-residency@ / msr@tsc@", 39 "MetricExpr": "cstate_core@c7\\-residency@ / msr@tsc@", 46 "MetricExpr": "cstate_pkg@c7\\-residency@ / msr@tsc@", 59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", 78 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde… 95 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh… [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	icx-metrics.json	4 "MetricExpr": "cstate_core@c1\\-residency@ / msr@tsc@", 11 "MetricExpr": "cstate_pkg@c2\\-residency@ / msr@tsc@", 18 "MetricExpr": "cstate_core@c6\\-residency@ / msr@tsc@", 25 "MetricExpr": "cstate_pkg@c6\\-residency@ / msr@tsc@", 58 … This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB", 65 …al number of completed instructions. This implies it missed in the DTLB and further levels of TLB", 72 …al number of completed instructions. This implies it missed in the DTLB and further levels of TLB", 145 …mplies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB", 152 …eted instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB", 312 …"BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Eng… [all …]

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