| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| H A D | ifu.json | 3 "PublicDescription": "I-Cache miss on an access from the prefetch block",
6 "BriefDescription": "I-Cache miss on an access from the prefetch block"
9 …"PublicDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l…
12 …"BriefDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l …
15 …"PublicDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 p…
18 …"BriefDescription": "Micro-predictor conditional/direction mispredict, with respect to. if3/if4 pr…
21 … "PublicDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor",
24 "BriefDescription": "Micro-predictor address mispredict, with respect to if3/if4 predictor"
27 "PublicDescription": "Micro-predictor hit with immediate redirect",
30 "BriefDescription": "Micro-predictor hit with immediate redirect"
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/ |
| H A D | cache.json | 111 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
114 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
117 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
120 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
129 "PublicDescription": "Level 1 PLD TLB refill",
132 "BriefDescription": "Level 1 PLD TLB refill"
135 …"PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwa…
138 …"BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwar…
141 "PublicDescription": "Level 1 TLB flush",
144 "BriefDescription": "Level 1 TLB flush"
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/ |
| H A D | metrics.json | 12 "BriefDescription": "Core-to-uncore bus utilization",
89 "BriefDescription": "Giga-floating point operations per second",
156 … "BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)",
162 "MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))",
163 "BriefDescription": "Of all the micro-operations issued, what proportion are lost",
169 "MetricExpr": "1 - OP_RETIRED / OP_SPEC",
170 …"BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed…
191 …BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss",
205 …"BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss",
212 …s the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication o…
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/ |
| H A D | metrics.json | 12 "BriefDescription": "Core-to-uncore bus utilization",
89 "BriefDescription": "Giga-floating point operations per second",
156 … "BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)",
162 "MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))",
163 "BriefDescription": "Of all the micro-operations issued, what proportion are lost",
169 "MetricExpr": "1 - OP_RETIRED / OP_SPEC",
170 …"BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed…
191 …"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss…
205 "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss",
212 …s the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication o…
[all …]
|
| /linux/arch/powerpc/platforms/8xx/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
33 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
39 MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.
42 bool "Analogue & Micro Adder 875"
45 This enables support for the Analogue & Micro Adder 875
56 menu "Freescale Ethernet driver platform-specific options"
76 Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
77 (often 2-nd UART) will not work if this is enabled.
83 Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
84 (often 1-nd UART) will not work if this is enabled.
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | metrics.json | 4 …"MetricExpr": "(100 * ((STALL_SLOT_BACKEND / (CPU_CYCLES * #slots)) - ((BR_MIS_PRED * 3) / CPU_CYC…
15 …0 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (((STALL_SLOT) if (strcmp_cpuid_str(0x410fd493) | strcmp…
48 …"BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions e…
55 …s the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication o…
57 "ScaleUnit": "1per TLB access"
61 …mp_cpuid_str(0x410fd490) ^ 1) else (STALL_SLOT_FRONTEND - CPU_CYCLES)) / (CPU_CYCLES * #slots)) - …
87 …"BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instruc…
94 … instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication o…
96 "ScaleUnit": "1per TLB access"
115 …1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indicat…
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/ |
| H A D | pipeline.json | 10 … DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre…
20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p…
25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
30 …"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instruc…
40 … "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
|
| /linux/tools/perf/pmu-events/arch/arm64/ |
| H A D | common-and-microarch.json | 15 "PublicDescription": "Attributable Level 1 instruction TLB refill",
18 "BriefDescription": "Attributable Level 1 instruction TLB refill"
33 "PublicDescription": "Attributable Level 1 data TLB refill",
36 "BriefDescription": "Attributable Level 1 data TLB refill"
129 "PublicDescription": "Attributable Level 1 data cache write-back",
132 "BriefDescription": "Attributable Level 1 data cache write-back"
147 "PublicDescription": "Attributable Level 2 data cache write-back",
150 "BriefDescription": "Attributable Level 2 data cache write-back"
219 "PublicDescription": "Attributable Level 1 data or unified TLB access",
222 "BriefDescription": "Attributable Level 1 data or unified TLB access"
[all …]
|
| /linux/tools/perf/Documentation/ |
| H A D | perf-arm-spe.txt | 1 perf-arm-spe(1)
5 ----
6 perf-arm-spe - Support for Arm Statistical Profiling Extension within Perf tools
9 -
[all...] |
| H A D | perf-amd-ibs.txt | 1 perf-amd-ibs(1)
5 ----
6 perf-amd-ibs - Support for AMD Instruction-Based Sampling (IBS) with perf tool
9 --------
11 'perf record' -e ibs_op//
12 'perf record' -e ibs_fetch//
15 -----------
17 Instruction-Based Sampling (IBS) provides precise Instruction Pointer (IP)
20 execution (micro-op execution to be precise) with details like d-cache
21 hit/miss, d-TLB hit/miss, cache miss latency, load/store data source, branch
[all …]
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_vm_tlb_fence.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2023 Advanced Micro Devices, Inc.
24 #include <linux/dma-fence.h>
43 return "amdgpu tlb fence"; in amdgpu_tlb_fence_get_driver_name()
48 return "amdgpu tlb timeline"; in amdgpu_tlb_fence_get_timeline_name()
56 if (f->dependency) { in amdgpu_tlb_fence_work()
57 dma_fence_wait(f->dependency, false); in amdgpu_tlb_fence_work()
58 dma_fence_put(f->dependency); in amdgpu_tlb_fence_work()
59 f->dependency = NULL; in amdgpu_tlb_fence_work()
62 r = amdgpu_gmc_flush_gpu_tlb_pasid(f->adev, f->pasid, 2, true, 0); in amdgpu_tlb_fence_work()
[all …]
|
| /linux/Documentation/devicetree/bindings/iommu/ |
| H A D | renesas,ipmmu-vmsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas VMSA-Compatible IOMMU
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 connected to the IPMMU through a port called micro-TLB.
20 - items:
21 - enum:
22 - renesas,ipmmu-r8a73a4 # R-Mobile APE6
[all …]
|
| H A D | qcom,apq8064-iommu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - David Heidelberg <david@ixit.cz>
16 outside of the CPU, each connected to the IOMMU through a port called micro-TLB.
20 const: qcom,apq8064-iommu
24 - description: interface clock for register accesses
25 - description: functional clock for bus accesses
27 clock-names:
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | snb-metrics.json | 4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
75 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
80 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/jaketown/ |
| H A D | jkt-metrics.json | 4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
75 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
80 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
[all …]
|
| /linux/drivers/perf/ |
| H A D | arm_v6_pmu.c | 1 // SPDX-License-Identifier: GPL-2.0
17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
19 * - disable the counter's interrupt generation (each counter has it's
24 * - enable the counter's interrupt generation.
25 * - set the new event type.
30 * ignoring that counter. When re-enabling, we have to reset the value and
103 * The ARM performance counters can count micro DTLB misses, micro ITLB
104 * misses and main TLB misses. There isn't an event for TLB misses, so
105 * use the micro misses here and if users want the main TLB misses they
174 struct hw_perf_event *hwc = &event->hw; in armv6pmu_read_counter()
[all …]
|
| /linux/arch/mips/mm/ |
| H A D | tlb-funcs.S | 6 * Micro-assembler generated tlb handler functions.
10 * Based on mm/page-funcs.c
12 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
|
| /linux/arch/arc/mm/ |
| H A D | tlbex.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TLB Exception Handling for ARC
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -MMU v1: moved out legacy code into a separate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of committing a D-TLB
14 * entry, so that it doesn't knock out its I-TLB entry
15 * -Some more fine tuning:
19 * -Practically rewrote the I/D TLB Miss handlers
26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
119 "MetricGroup": "tlb"
148 "BriefDescription": "Micro-ops Dispatched",
160 "BriefDescription": "Micro-ops Retired"
168 "ScaleUnit": "3e-5MiB"
177 "ScaleUnit": "6.1e-5MiB"
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen2/ |
| H A D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
119 "MetricGroup": "tlb"
148 "BriefDescription": "Micro-ops Dispatched",
160 "BriefDescription": "Micro-ops Retired"
168 "ScaleUnit": "3e-5MiB"
177 "ScaleUnit": "6.1e-5MiB"
|
| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | hsx-metrics.json | 4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
79 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
86 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
105 …plies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | bdx-metrics.json | 4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
79 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
86 …l number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
105 …plies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
[all …]
|
| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_gt_types.h | 1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2022-2023 Intel Corporation
61 * need to explicitly re-steer reads of registers of the other type.
63 * Only the replication types that may need additional non-default steering
76 * will always return a non-terminated value at instance (0, 0). We'll
83 * it's sufficient to keep the HW-default for the selector, or only
93 const struct xe_gt * : (const struct xe_tile *)((gt__)->tile), \
94 struct xe_gt * : (gt__)->tile)
98 const struct xe_gt * : (const struct xe_device *)(gt_to_tile(gt__)->xe), \
99 struct xe_gt * : gt_to_tile(gt__)->xe)
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | hsw-metrics.json | 4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
78 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
96 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | ivb-metrics.json | 4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
78 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
96 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
[all …]
|