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/linux/drivers/gpu/drm/i915/display/
H A Dintel_plane_initial.c1 // SPDX-License-Identifier: MIT
23 struct drm_i915_private *i915 = to_i915(this->base.dev); in intel_reuse_initial_plane_obj()
26 for_each_intel_crtc(&i915->drm, crtc) { in intel_reuse_initial_plane_obj()
28 to_intel_plane(crtc->base.primary); in intel_reuse_initial_plane_obj()
30 to_intel_plane_state(plane->base.state); in intel_reuse_initial_plane_obj()
32 to_intel_crtc_state(crtc->base.state); in intel_reuse_initial_plane_obj()
34 if (!crtc_state->uapi.active) in intel_reuse_initial_plane_obj()
37 if (!plane_state->ggtt_vma) in intel_reuse_initial_plane_obj()
40 if (plane_configs[this->pipe].base == plane_configs[crtc->pipe].base) { in intel_reuse_initial_plane_obj()
41 *fb = plane_state->hw.fb; in intel_reuse_initial_plane_obj()
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dheadc57d.c33 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in headc57d_display_id()
39 PUSH_NVSQ(push, NVC57D, 0x2020 + (head->base.index * 0x400), display_id); in headc57d_display_id()
46 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in headc57d_or()
47 const int i = head->base.index; in headc57d_or()
54 switch (asyh->or.depth) { in headc57d_or()
60 depth = asyh->or.depth; in headc57d_or()
69 NVVAL(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) | in headc57d_or()
70 NVVAL(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) | in headc57d_or()
71 NVVAL(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) | in headc57d_or()
81 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in headc57d_procamp()
[all …]
H A Dhead507d.c32 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in head507d_procamp()
33 const int i = head->base.index; in head507d_procamp()
42 NVVAL(NV507D, HEAD_SET_PROCAMP, SAT_COS, asyh->procamp.sat.cos) | in head507d_procamp()
43 NVVAL(NV507D, HEAD_SET_PROCAMP, SAT_SINE, asyh->procamp.sat.sin) | in head507d_procamp()
51 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in head507d_dither()
52 const int i = head->base.index; in head507d_dither()
59 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in head507d_dither()
60 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in head507d_dither()
61 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in head507d_dither()
69 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in head507d_ovly()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gpuvm.c1 // SPDX-License-Identifier: MIT
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
23 #include <linux/dma-buf.h>
73 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
78 struct kgd_mem *mem) in kfd_mem_is_attached() argument
82 list_for_each_entry(entry, &mem->attachments, list) in kfd_mem_is_attached()
83 if (entry->bo_va->base.vm == avm) in kfd_mem_is_attached()
90 * reuse_dmamap() - Check whether adev can share the original
104 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) || in reuse_dmamap()
105 (adev->dev->iommu_group == bo_adev->dev->iommu_group); in reuse_dmamap()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
H A Dnv50.c32 nv50_bar_flush(struct nvkm_bar *base) in nv50_bar_flush() argument
34 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_flush()
35 struct nvkm_device *device = bar->base.subdev.device; in nv50_bar_flush()
37 spin_lock_irqsave(&bar->base.lock, flags); in nv50_bar_flush()
43 spin_unlock_irqrestore(&bar->base.lock, flags); in nv50_bar_flush()
47 nv50_bar_bar1_vmm(struct nvkm_bar *base) in nv50_bar_bar1_vmm() argument
49 return nv50_bar(base)->bar1_vmm; in nv50_bar_bar1_vmm()
53 nv50_bar_bar1_wait(struct nvkm_bar *base) in nv50_bar_bar1_wait() argument
55 nvkm_bar_flush(base); in nv50_bar_bar1_wait()
61 nvkm_wr32(bar->subdev.device, 0x001708, 0x00000000); in nv50_bar_bar1_fini()
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/linux/drivers/watchdog/
H A Dmenz69_wdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Watchdog driver for the MEN z069 IP-Core
15 void __iomem *base; member
16 struct resource *mem; member
39 val = readw(drv->base + MEN_Z069_WTR); in men_z069_wdt_start()
41 writew(val, drv->base + MEN_Z069_WTR); in men_z069_wdt_start()
51 val = readw(drv->base + MEN_Z069_WTR); in men_z069_wdt_stop()
53 writew(val, drv->base + MEN_Z069_WTR); in men_z069_wdt_stop()
64 val = readw(drv->base + MEN_Z069_WVR); in men_z069_wdt_ping()
66 writew(val, drv->base + MEN_Z069_WVR); in men_z069_wdt_ping()
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/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_stolen.c2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008-2012 Intel Corporation
46 if (!drm_mm_initialized(&i915->mm.stolen)) in i915_gem_stolen_insert_node_in_range()
47 return -ENODEV; in i915_gem_stolen_insert_node_in_range()
53 mutex_lock(&i915->mm.stolen_lock); in i915_gem_stolen_insert_node_in_range()
54 ret = drm_mm_insert_node_in_range(&i915->mm.stolen, node, in i915_gem_stolen_insert_node_in_range()
57 mutex_unlock(&i915->mm.stolen_lock); in i915_gem_stolen_insert_node_in_range()
75 mutex_lock(&i915->mm.stolen_lock); in i915_gem_stolen_remove_node()
77 mutex_unlock(&i915->mm.stolen_lock); in i915_gem_stolen_remove_node()
82 return (dsm->start != 0 || HAS_LMEMBAR_SMEM_STOLEN(i915)) && dsm->end > dsm->start; in valid_stolen_size()
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/linux/drivers/gpu/drm/ttm/
H A Dttm_bo_util.c1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
4 * Copyright (c) 2007-2009 VMware, Inc., Palo Alto, CA., USA
21 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
29 * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
41 struct ttm_buffer_object base; member
46 struct ttm_resource *mem) in ttm_mem_io_reserve() argument
48 if (mem->bus.offset || mem->bus.addr) in ttm_mem_io_reserve()
51 mem->bus.is_iomem = false; in ttm_mem_io_reserve()
52 if (!bdev->funcs->io_mem_reserve) in ttm_mem_io_reserve()
55 return bdev->funcs->io_mem_reserve(bdev, mem); in ttm_mem_io_reserve()
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/linux/drivers/spi/
H A Dspi-sn-f-ospi.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/spi/spi-mem.h>
111 void __iomem *base; member
119 return (op->dummy.nbytes * 8) / op->dummy.buswidth; in f_ospi_get_dummy_cycle()
125 ospi->base + OSPI_IRQ); in f_ospi_clear_irq()
132 val = readl(ospi->base + OSPI_IRQ_STAT_EN); in f_ospi_enable_irq_status()
134 writel(val, ospi->base + OSPI_IRQ_STAT_EN); in f_ospi_enable_irq_status()
141 val = readl(ospi->base + OSPI_IRQ_STAT_EN); in f_ospi_disable_irq_status()
143 writel(val, ospi->base + OSPI_IRQ_STAT_EN); in f_ospi_disable_irq_status()
150 val = readl(ospi->base + OSPI_IRQ_SIG_EN); in f_ospi_disable_irq_output()
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H A Dspi-intel.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016 - 2022, Intel Corporation
13 #include <linux/mtd/spi-nor.h>
17 #include <linux/spi/spi-mem.h>
19 #include "spi-intel.h"
21 /* Offsets are from @ispi->base */
60 /* Offset is from @ispi->pregs */
68 /* Offsets are from @ispi->sregs */
140 * struct intel_spi - Driver private data
143 * @base: Beginning of MMIO space
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/linux/drivers/net/can/sja1000/
H A Dsja1000_isa.c1 // SPDX-License-Identifier: GPL-2.0-only
24 MODULE_DESCRIPTION("Socket-CAN driver for SJA1000 on the ISA bus");
32 static unsigned long mem[MAXDEV]; variable
35 static unsigned char cdr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
36 static unsigned char ocr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
37 static int indirect[MAXDEV] = {[0 ... (MAXDEV - 1)] = -1};
43 module_param_hw_array(mem, ulong, iomem, NULL, 0444);
44 MODULE_PARM_DESC(mem, "I/O memory address");
71 return readb(priv->reg_base + reg); in sja1000_isa_mem_read_reg()
77 writeb(val, priv->reg_base + reg); in sja1000_isa_mem_write_reg()
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/linux/drivers/iio/adc/
H A Dmen_z188_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
25 struct resource *mem; member
26 void __iomem *base; member
59 tmp = readw(adc->base + chan->channel * 4); in z188_iio_read_raw()
62 dev_info(&iio_dev->dev, in z188_iio_read_raw()
64 chan->channel); in z188_iio_read_raw()
65 return -EIO; in z188_iio_read_raw()
71 ret = -EINVAL; in z188_iio_read_raw()
105 struct resource *mem; in men_z188_probe() local
108 indio_dev = devm_iio_device_alloc(&dev->dev, sizeof(struct z188_adc)); in men_z188_probe()
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/linux/drivers/pci/controller/
H A Dpci-v3-semi.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
134 /* PCI BASE bits (PCI -> Local Bus) */
141 /* PCI MAP bits (PCI -> Local bus) */
150 /* LB_BASE0,1 bits (Local bus -> PCI) */
172 /* LB_MAP0,1 bits (Local bus -> PCI) */
185 /* LB_BASE2 bits (Local bus -> PCI IO) */
192 /* LB_MAP2 bits (Local bus -> PCI IO) */
229 /* ARM Integrator-specific extended control registers */
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/linux/drivers/net/can/cc770/
H A Dcc770_isa.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Bosch CC770 and Intel AN82527 CAN controllers on the ISA or PC-104 bus.
17 * insmod cc770_isa.ko mem=0xd1000,0xd1000 irq=7,11
32 * Note: for clk, cir, bcr and cor, the first argument re-defines the
35 * insmod cc770_isa.ko mem=0xd1000,0xd1000 irq=7,11 clk=24000000
39 * insmod cc770_isa.ko mem=0xd1000,0xd1000 irq=7,11 clk=24000000,24000000
61 MODULE_DESCRIPTION("Socket-CAN driver for CC770 on the ISA bus");
69 static unsigned long mem[MAXDEV]; variable
72 static u8 cir[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
73 static u8 cor[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff};
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/linux/arch/arm/mm/
H A Dpmsa-v7.c20 phys_addr_t base; member
25 static struct region __initdata mem[MPU_MAX_REGIONS]; variable
52 /* Data-side / unified region attributes */
66 /* Region base address register */
76 /* Optional instruction-side region attributes */
78 /* I-side Region access control register */
84 /* I-side Region size register */
90 /* I-side Region base address register */
108 /* Data-side / unified region attributes */
126 /* Region base address register */
[all …]
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_fw.c1 // SPDX-License-Identifier: GPL-2.0 or MIT
9 #include <linux/dma-mapping.h>
12 #include <linux/iosys-map.h>
36 * struct panthor_fw_binary_hdr - Firmware binary header.
64 * enum panthor_fw_binary_entry_type - Firmware binary entry type
67 /** @CSF_FW_BINARY_ENTRY_TYPE_IFACE: Host <-> FW interface. */
73 /** @CSF_FW_BINARY_ENTRY_TYPE_FUTF_TEST: Unit-tests. */
110 * struct panthor_fw_binary_section_entry_hdr - Describes a section of FW binary
136 * struct panthor_fw_binary_iter - Firmware binary iterator
152 * struct panthor_fw_section - FW section
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/linux/kernel/module/
H A Dkdb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * kdb_lsmod - This function implements the 'lsmod' command. Lists
26 if (mod->state == MODULE_STATE_UNFORMED) in kdb_lsmod()
29 kdb_printf("%-20s%8u", mod->name, mod->mem[MOD_TEXT].size); in kdb_lsmod()
30 kdb_printf("/%8u", mod->mem[MOD_RODATA].size); in kdb_lsmod()
31 kdb_printf("/%8u", mod->mem[MOD_RO_AFTER_INIT].size); in kdb_lsmod()
32 kdb_printf("/%8u", mod->mem[MOD_DATA].size); in kdb_lsmod()
38 if (mod->state == MODULE_STATE_GOING) in kdb_lsmod()
40 else if (mod->state == MODULE_STATE_COMING) in kdb_lsmod()
44 kdb_printf(" 0x%px", mod->mem[MOD_TEXT].base); in kdb_lsmod()
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/linux/arch/powerpc/boot/
H A Dcuboot-pq2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Old U-boot compatibility for PowerQUICC II
15 #include "fsl-soc.h"
25 u32 base; /* must be zero */ member
40 /* Different versions of u-boot put the BCSR in different places, and
44 * For any node defined as compatible with fsl,pq2-localbus,
58 if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus")) in update_cs_ranges()
80 u32 base, option; in update_cs_ranges() local
85 if (cs_ranges_buf[i].base != 0) in update_cs_ranges()
88 base = in_be32(&ctrl_addr[cs * 2]); in update_cs_ranges()
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/linux/drivers/video/
H A Daperture.c1 // SPDX-License-Identifier: MIT
21 * graphics drivers, such as EFI-GOP or VESA, early during the boot process.
23 * hardware-specific driver. To take over the device, the dedicated driver
25 * ownership of framebuffer memory and hand-over between drivers.
32 * .. code-block:: c
36 * struct resource *mem;
37 * resource_size_t base, size;
40 * mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
41 * if (!mem)
42 * return -ENODEV;
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/linux/drivers/of/
H A Dfdt.c1 // SPDX-License-Identifier: GPL-2.0
43 * of_fdt_limit_memory - limit the number of regions in the /memory node
82 static void *unflatten_dt_alloc(void **mem, unsigned long size, in unflatten_dt_alloc() argument
87 *mem = PTR_ALIGN(*mem, align); in unflatten_dt_alloc()
88 res = *mem; in unflatten_dt_alloc()
89 *mem += size; in unflatten_dt_alloc()
96 void **mem, in populate_properties() argument
105 pprev = &np->properties; in populate_properties()
127 pp = unflatten_dt_alloc(mem, sizeof(struct property), in populate_properties()
133 * ePAPR-style "phandle" properties, or the in populate_properties()
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/linux/tools/testing/selftests/riscv/hwprobe/
H A Dcbo.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Run with 'taskset -c <cpu-list> cbo' to only execute hwprobe on a
24 static char mem[4096] __aligned(4096) = { [0 ... 4095] = 0xa5 }; variable
30 unsigned long *regs = (unsigned long *)&((ucontext_t *)context)->uc_mcontext; in sigill_handler()
39 #define cbo_insn(base, fn) \ argument
45 : : "r" (base), "i" (fn), "i" (MK_CBO(fn)) : "a0", "a1", "memory"); \
48 static void cbo_inval(char *base) { cbo_insn(base, 0); } in cbo_inval() argument
49 static void cbo_clean(char *base) { cbo_insn(base, 1); } in cbo_clean() argument
50 static void cbo_flush(char *base) { cbo_insn(base, 2); } in cbo_flush() argument
51 static void cbo_zero(char *base) { cbo_insn(base, 4); } in cbo_zero() argument
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/linux/drivers/net/ethernet/amd/
H A Dsun3lance.c76 MODULE_PARM_DESC(lance_debug, "SUN3 Lance debug level (0-3)");
77 MODULE_DESCRIPTION("Sun3/Sun3x on-board LANCE Ethernet driver");
97 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
101 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
107 #define PKTBUF_ADDR(head) (void *)((unsigned long)(MEM) | (head)->base)
112 unsigned short base; /* Low word of base addr */ member
114 unsigned char base_hi; /* High word of base addr (unused) */
120 unsigned short base; /* Low word of base addr */ member
122 unsigned char base_hi; /* High word of base addr (unused) */
129 unsigned short mode; /* Pre-set mode */
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fault/
H A Dgv100.c34 struct nvkm_fault_buffer *buffer = fault->buffer[0]; in gv100_fault_buffer_process()
35 struct nvkm_device *device = fault->subdev.device; in gv100_fault_buffer_process()
36 struct nvkm_memory *mem = buffer->mem; in gv100_fault_buffer_process() local
37 u32 get = nvkm_rd32(device, buffer->get); in gv100_fault_buffer_process()
38 u32 put = nvkm_rd32(device, buffer->put); in gv100_fault_buffer_process()
42 nvkm_kmap(mem); in gv100_fault_buffer_process()
44 const u32 base = get * buffer->fault->func->buffer.entry_size; in gv100_fault_buffer_process() local
45 const u32 instlo = nvkm_ro32(mem, base + 0x00); in gv100_fault_buffer_process()
46 const u32 insthi = nvkm_ro32(mem, base + 0x04); in gv100_fault_buffer_process()
47 const u32 addrlo = nvkm_ro32(mem, base + 0x08); in gv100_fault_buffer_process()
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_ttm_stolen_mgr.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021-2023 Intel Corporation
4 * Copyright (C) 2021-2002 Red Hat
30 struct xe_ttm_vram_mgr base; member
32 /* PCI base offset */
34 /* GPU base offset */
43 return container_of(man, struct xe_ttm_stolen_mgr, base.manager); in to_stolen_mgr()
47 * xe_ttm_stolen_cpu_access_needs_ggtt() - If we can't directly CPU access
64 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); in detect_bar2_dgfx()
69 tile_offset = tile->mem.vram.io_start - xe->mem.vram.io_start; in detect_bar2_dgfx()
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/linux/drivers/mfd/
H A Dvexpress-sysreg.c1 // SPDX-License-Identifier: GPL-2.0-only
43 .base = -1,
49 .base = -1,
55 .base = -1,
61 .name = "basic-mmio-gpio",
62 .of_compatible = "arm,vexpress-sysreg,sys_led",
68 .name = "basic-mmio-gpio",
69 .of_compatible = "arm,vexpress-sysreg,sys_mci",
75 .name = "basic-mmio-gpio",
76 .of_compatible = "arm,vexpress-sysreg,sys_flash",
[all …]

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