Lines Matching +full:mem +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
134 /* PCI BASE bits (PCI -> Local Bus) */
141 /* PCI MAP bits (PCI -> Local bus) */
150 /* LB_BASE0,1 bits (Local bus -> PCI) */
172 /* LB_MAP0,1 bits (Local bus -> PCI) */
185 /* LB_BASE2 bits (Local bus -> PCI IO) */
192 /* LB_MAP2 bits (Local bus -> PCI IO) */
229 /* ARM Integrator-specific extended control registers */
238 void __iomem *base; member
257 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
258 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
259 * 60000000 - 60FFFFFF PCI IO. 16M
260 * 61000000 - 61FFFFFF PCI Configuration. 16M
268 * Normally these spaces are mapped using the following base registers:
270 * Usage Local Bus Memory Base/Map registers used
272 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
273 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
274 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
275 * Cfg 61000000 - 61FFFFFF
281 * Usage Local Bus Memory Base/Map registers used
283 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
284 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
285 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
286 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
290 * each of the BASE/MAP pairs in turn (in ascending register number
313 struct v3_pci *v3 = bus->sysdata; in v3_map_bus()
316 busnr = bus->number; in v3_map_bus()
323 * build the PCI configuration "address" with one-hot in in v3_map_bus()
324 * A31-A11 in v3_map_bus()
337 mapaddress |= BIT(slot - 5); in v3_map_bus()
362 * prefetchable), this frees up base1 for re-use by in v3_map_bus()
365 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_map_bus()
367 v3->base + V3_LB_BASE0); in v3_map_bus()
371 * The config mem is always 16MB. in v3_map_bus()
373 writel(v3_addr_to_lb_base(v3->config_mem) | in v3_map_bus()
375 v3->base + V3_LB_BASE1); in v3_map_bus()
376 writew(mapaddress, v3->base + V3_LB_MAP1); in v3_map_bus()
378 return v3->config_base + address + offset; in v3_map_bus()
386 writel(v3_addr_to_lb_base(v3->pre_mem) | in v3_unmap_bus()
389 v3->base + V3_LB_BASE1); in v3_unmap_bus()
390 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | in v3_unmap_bus()
392 v3->base + V3_LB_MAP1); in v3_unmap_bus()
397 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_unmap_bus()
399 v3->base + V3_LB_BASE0); in v3_unmap_bus()
405 struct v3_pci *v3 = bus->sysdata; in v3_pci_read_config()
408 dev_dbg(&bus->dev, in v3_pci_read_config()
419 struct v3_pci *v3 = bus->sysdata; in v3_pci_write_config()
422 dev_dbg(&bus->dev, in v3_pci_write_config()
439 struct device *dev = v3->dev; in v3_irq()
442 status = readw(v3->base + V3_PCI_STAT); in v3_irq()
451 writew(status, v3->base + V3_PCI_STAT); in v3_irq()
453 status = readb(v3->base + V3_LB_ISTAT); in v3_irq()
457 dev_err(dev, "PCI target LB->PCI READ abort interrupt\n"); in v3_irq()
459 dev_err(dev, "PCI target LB->PCI WRITE abort interrupt\n"); in v3_irq()
471 writeb(0, v3->base + V3_LB_ISTAT); in v3_irq()
472 if (v3->map) in v3_irq()
473 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, in v3_irq()
484 v3->map = in v3_integrator_init()
485 syscon_regmap_lookup_by_compatible("arm,integrator-ap-syscon"); in v3_integrator_init()
486 if (IS_ERR(v3->map)) { in v3_integrator_init()
487 dev_err(v3->dev, "no syscon\n"); in v3_integrator_init()
488 return -ENODEV; in v3_integrator_init()
491 regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val); in v3_integrator_init()
493 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, in v3_integrator_init()
501 /* Set the physical base for the controller itself */ in v3_integrator_init()
502 writel(0x6200, v3->base + V3_LB_IO_BASE); in v3_integrator_init()
506 writeb(0xaa, v3->base + V3_MAIL_DATA); in v3_integrator_init()
507 writeb(0x55, v3->base + V3_MAIL_DATA + 4); in v3_integrator_init()
508 } while (readb(v3->base + V3_MAIL_DATA) != 0xaa && in v3_integrator_init()
509 readb(v3->base + V3_MAIL_DATA) != 0x55); in v3_integrator_init()
512 dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n"); in v3_integrator_init()
521 struct device *dev = v3->dev; in v3_pci_setup_resource()
522 struct resource *mem; in v3_pci_setup_resource() local
525 switch (resource_type(win->res)) { in v3_pci_setup_resource()
527 io = win->res; in v3_pci_setup_resource()
529 /* Setup window 2 - PCI I/O */ in v3_pci_setup_resource()
530 writel(v3_addr_to_lb_base2(pci_pio_to_address(io->start)) | in v3_pci_setup_resource()
532 v3->base + V3_LB_BASE2); in v3_pci_setup_resource()
533 writew(v3_addr_to_lb_map2(io->start - win->offset), in v3_pci_setup_resource()
534 v3->base + V3_LB_MAP2); in v3_pci_setup_resource()
537 mem = win->res; in v3_pci_setup_resource()
538 if (mem->flags & IORESOURCE_PREFETCH) { in v3_pci_setup_resource()
539 mem->name = "V3 PCI PRE-MEM"; in v3_pci_setup_resource()
540 v3->pre_mem = mem->start; in v3_pci_setup_resource()
541 v3->pre_bus_addr = mem->start - win->offset; in v3_pci_setup_resource()
542 dev_dbg(dev, "PREFETCHABLE MEM window %pR, bus addr %pap\n", in v3_pci_setup_resource()
543 mem, &v3->pre_bus_addr); in v3_pci_setup_resource()
544 if (resource_size(mem) != SZ_256M) { in v3_pci_setup_resource()
546 return -EINVAL; in v3_pci_setup_resource()
548 if (v3->non_pre_mem && in v3_pci_setup_resource()
549 (mem->start != v3->non_pre_mem + SZ_256M)) { in v3_pci_setup_resource()
551 "prefetchable memory is not adjacent to non-prefetchable memory\n"); in v3_pci_setup_resource()
552 return -EINVAL; in v3_pci_setup_resource()
554 /* Setup window 1 - PCI prefetchable memory */ in v3_pci_setup_resource()
555 writel(v3_addr_to_lb_base(v3->pre_mem) | in v3_pci_setup_resource()
559 v3->base + V3_LB_BASE1); in v3_pci_setup_resource()
560 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | in v3_pci_setup_resource()
562 v3->base + V3_LB_MAP1); in v3_pci_setup_resource()
564 mem->name = "V3 PCI NON-PRE-MEM"; in v3_pci_setup_resource()
565 v3->non_pre_mem = mem->start; in v3_pci_setup_resource()
566 v3->non_pre_bus_addr = mem->start - win->offset; in v3_pci_setup_resource()
567 dev_dbg(dev, "NON-PREFETCHABLE MEM window %pR, bus addr %pap\n", in v3_pci_setup_resource()
568 mem, &v3->non_pre_bus_addr); in v3_pci_setup_resource()
569 if (resource_size(mem) != SZ_256M) { in v3_pci_setup_resource()
571 "non-prefetchable memory range is not 256MB\n"); in v3_pci_setup_resource()
572 return -EINVAL; in v3_pci_setup_resource()
574 /* Setup window 0 - PCI non-prefetchable memory */ in v3_pci_setup_resource()
575 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_pci_setup_resource()
578 v3->base + V3_LB_BASE0); in v3_pci_setup_resource()
579 writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) | in v3_pci_setup_resource()
581 v3->base + V3_LB_MAP0); in v3_pci_setup_resource()
588 resource_type(win->res)); in v3_pci_setup_resource()
599 struct device *dev = v3->dev; in v3_get_dma_range_config()
600 u64 cpu_addr = entry->res->start; in v3_get_dma_range_config()
601 u64 cpu_end = entry->res->end; in v3_get_dma_range_config()
602 u64 pci_end = cpu_end - entry->offset; in v3_get_dma_range_config()
603 u64 pci_addr = entry->res->start - entry->offset; in v3_get_dma_range_config()
608 return -EINVAL; in v3_get_dma_range_config()
615 return -EINVAL; in v3_get_dma_range_config()
619 switch (resource_size(entry->res)) { in v3_get_dma_range_config()
657 dev_err(v3->dev, "illegal dma memory chunk size\n"); in v3_get_dma_range_config()
658 return -EINVAL; in v3_get_dma_range_config()
664 "DMA MEM CPU: 0x%016llx -> 0x%016llx => " in v3_get_dma_range_config()
665 "PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n", in v3_get_dma_range_config()
677 struct device *dev = v3->dev; in v3_pci_parse_map_dma_ranges()
681 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in v3_pci_parse_map_dma_ranges()
690 writel(pci_base, v3->base + V3_PCI_BASE0); in v3_pci_parse_map_dma_ranges()
691 writel(pci_map, v3->base + V3_PCI_MAP0); in v3_pci_parse_map_dma_ranges()
693 writel(pci_base, v3->base + V3_PCI_BASE1); in v3_pci_parse_map_dma_ranges()
694 writel(pci_map, v3->base + V3_PCI_MAP1); in v3_pci_parse_map_dma_ranges()
706 struct device *dev = &pdev->dev; in v3_pci_probe()
707 struct device_node *np = dev->of_node; in v3_pci_probe()
719 return -ENOMEM; in v3_pci_probe()
721 host->ops = &v3_pci_ops; in v3_pci_probe()
723 host->sysdata = v3; in v3_pci_probe()
724 v3->dev = dev; in v3_pci_probe()
738 v3->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); in v3_pci_probe()
739 if (IS_ERR(v3->base)) in v3_pci_probe()
740 return PTR_ERR(v3->base); in v3_pci_probe()
742 * The hardware has a register with the physical base address in v3_pci_probe()
746 if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16)) in v3_pci_probe()
748 readl(v3->base + V3_LB_IO_BASE), regs); in v3_pci_probe()
753 dev_err(dev, "config mem is not 16MB!\n"); in v3_pci_probe()
754 return -EINVAL; in v3_pci_probe()
756 v3->config_mem = regs->start; in v3_pci_probe()
757 v3->config_base = devm_ioremap_resource(dev, regs); in v3_pci_probe()
758 if (IS_ERR(v3->config_base)) in v3_pci_probe()
759 return PTR_ERR(v3->config_base); in v3_pci_probe()
778 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK) in v3_pci_probe()
779 writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM); in v3_pci_probe()
782 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
784 writew(val, v3->base + V3_PCI_CMD); in v3_pci_probe()
787 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
789 writew(val, v3->base + V3_SYSTEM); in v3_pci_probe()
792 val = readw(v3->base + V3_PCI_CFG); in v3_pci_probe()
794 writew(val, v3->base + V3_PCI_CFG); in v3_pci_probe()
797 val = readw(v3->base + V3_LB_CFG); in v3_pci_probe()
802 writew(val, v3->base + V3_LB_CFG); in v3_pci_probe()
805 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
807 writew(val, v3->base + V3_PCI_CMD); in v3_pci_probe()
810 resource_list_for_each_entry(win, &host->windows) { in v3_pci_probe()
826 writel(0x00000000, v3->base + V3_PCI_IO_BASE); in v3_pci_probe()
834 writew(val, v3->base + V3_PCI_CFG); in v3_pci_probe()
845 v3->base + V3_FIFO_PRIORITY); in v3_pci_probe()
852 writeb(0, v3->base + V3_LB_ISTAT); in v3_pci_probe()
853 val = readw(v3->base + V3_LB_CFG); in v3_pci_probe()
855 writew(val, v3->base + V3_LB_CFG); in v3_pci_probe()
857 v3->base + V3_LB_IMASK); in v3_pci_probe()
860 if (of_device_is_compatible(np, "arm,integrator-ap-pci")) { in v3_pci_probe()
866 /* Post-init: enable PCI memory and invalidate (master already on) */ in v3_pci_probe()
867 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
869 writew(val, v3->base + V3_PCI_CMD); in v3_pci_probe()
872 writeb(0, v3->base + V3_LB_ISTAT); in v3_pci_probe()
875 v3->base + V3_LB_IMASK); in v3_pci_probe()
878 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
880 writew(val, v3->base + V3_SYSTEM); in v3_pci_probe()
883 * Re-lock the system register. in v3_pci_probe()
885 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
887 writew(val, v3->base + V3_SYSTEM); in v3_pci_probe()
894 .compatible = "v3,v360epc-pci",
901 .name = "pci-v3-semi",