1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2016 - 2022, Intel Corporation
13 #include <linux/mtd/spi-nor.h>
17 #include <linux/spi/spi-mem.h>
19 #include "spi-intel.h"
21 /* Offsets are from @ispi->base */
60 /* Offset is from @ispi->pregs */
68 /* Offsets are from @ispi->sregs */
140  * struct intel_spi - Driver private data
143  * @base: Beginning of MMIO space
156  * @mem_ops: Pointer to SPI MEM ops supported by the controller
161 	void __iomem *base;  member
180 		       const struct spi_mem *mem,
194 	dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));  in intel_spi_dump_regs()
196 	value = readl(ispi->base + HSFSTS_CTL);  in intel_spi_dump_regs()
197 	dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);  in intel_spi_dump_regs()
199 		dev_dbg(ispi->dev, "-> Locked\n");  in intel_spi_dump_regs()
201 	dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));  in intel_spi_dump_regs()
202 	dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));  in intel_spi_dump_regs()
205 		dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",  in intel_spi_dump_regs()
206 			i, readl(ispi->base + FDATA(i)));  in intel_spi_dump_regs()
208 	dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));  in intel_spi_dump_regs()
210 	for (i = 0; i < ispi->nregions; i++)  in intel_spi_dump_regs()
211 		dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,  in intel_spi_dump_regs()
212 			readl(ispi->base + FREG(i)));  in intel_spi_dump_regs()
213 	for (i = 0; i < ispi->pr_num; i++)  in intel_spi_dump_regs()
214 		dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,  in intel_spi_dump_regs()
215 			readl(ispi->pregs + PR(i)));  in intel_spi_dump_regs()
217 	if (ispi->sregs) {  in intel_spi_dump_regs()
218 		value = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_dump_regs()
219 		dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);  in intel_spi_dump_regs()
220 		dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",  in intel_spi_dump_regs()
221 			readl(ispi->sregs + PREOP_OPTYPE));  in intel_spi_dump_regs()
222 		dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",  in intel_spi_dump_regs()
223 			readl(ispi->sregs + OPMENU0));  in intel_spi_dump_regs()
224 		dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",  in intel_spi_dump_regs()
225 			readl(ispi->sregs + OPMENU1));  in intel_spi_dump_regs()
228 	dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));  in intel_spi_dump_regs()
229 	dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));  in intel_spi_dump_regs()
231 	dev_dbg(ispi->dev, "Protected regions:\n");  in intel_spi_dump_regs()
232 	for (i = 0; i < ispi->pr_num; i++) {  in intel_spi_dump_regs()
233 		u32 base, limit;  in intel_spi_dump_regs()  local
235 		value = readl(ispi->pregs + PR(i));  in intel_spi_dump_regs()
240 		base = value & PR_BASE_MASK;  in intel_spi_dump_regs()
242 		dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",  in intel_spi_dump_regs()
243 			i, base << 12, (limit << 12) | 0xfff,  in intel_spi_dump_regs()
247 	dev_dbg(ispi->dev, "Flash regions:\n");  in intel_spi_dump_regs()
248 	for (i = 0; i < ispi->nregions; i++) {  in intel_spi_dump_regs()
249 		u32 region, base, limit;  in intel_spi_dump_regs()  local
251 		region = readl(ispi->base + FREG(i));  in intel_spi_dump_regs()
252 		base = region & FREG_BASE_MASK;  in intel_spi_dump_regs()
255 		if (base >= limit || (i > 0 && limit == 0))  in intel_spi_dump_regs()
256 			dev_dbg(ispi->dev, " %02d disabled\n", i);  in intel_spi_dump_regs()
258 			dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",  in intel_spi_dump_regs()
259 				i, base << 12, (limit << 12) | 0xfff);  in intel_spi_dump_regs()
262 	dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",  in intel_spi_dump_regs()
263 		ispi->swseq_reg ? 'S' : 'H');  in intel_spi_dump_regs()
264 	dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",  in intel_spi_dump_regs()
265 		ispi->swseq_erase ? 'S' : 'H');  in intel_spi_dump_regs()
275 		return -EINVAL;  in intel_spi_read_block()
279 		memcpy_fromio(buf, ispi->base + FDATA(i), bytes);  in intel_spi_read_block()
280 		size -= bytes;  in intel_spi_read_block()
296 		return -EINVAL;  in intel_spi_write_block()
300 		memcpy_toio(ispi->base + FDATA(i), buf, bytes);  in intel_spi_write_block()
301 		size -= bytes;  in intel_spi_write_block()
313 	return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,  in intel_spi_wait_hw_busy()
322 	return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,  in intel_spi_wait_sw_busy()
329 	if (!ispi->info->set_writeable)  in intel_spi_set_writeable()
332 	return ispi->info->set_writeable(ispi->base, ispi->info->data);  in intel_spi_set_writeable()
340 	if (ispi->locked) {  in intel_spi_opcode_index()
341 		for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)  in intel_spi_opcode_index()
342 			if (ispi->opcodes[i] == opcode)  in intel_spi_opcode_index()
345 		return -EINVAL;  in intel_spi_opcode_index()
349 	writel(opcode, ispi->sregs + OPMENU0);  in intel_spi_opcode_index()
350 	preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
351 	writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
362 	if (!iop->replacement_op)  in intel_spi_hw_cycle()
363 		return -EINVAL;  in intel_spi_hw_cycle()
365 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
367 	val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;  in intel_spi_hw_cycle()
370 	val |= iop->replacement_op;  in intel_spi_hw_cycle()
371 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
377 	status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
379 		return -EIO;  in intel_spi_hw_cycle()
381 		return -EACCES;  in intel_spi_hw_cycle()
401 	atomic_preopcode = ispi->atomic_preopcode;  in intel_spi_sw_cycle()
402 	ispi->atomic_preopcode = 0;  in intel_spi_sw_cycle()
406 		val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;  in intel_spi_sw_cycle()
417 			preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_sw_cycle()
423 				return -EINVAL;  in intel_spi_sw_cycle()
430 			return -EINVAL;  in intel_spi_sw_cycle()
433 	writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
439 	status = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
441 		return -EIO;  in intel_spi_sw_cycle()
443 		return -EACCES;  in intel_spi_sw_cycle()
449 			       const struct spi_mem *mem)  in intel_spi_chip_addr()  argument
452 	if (!mem)  in intel_spi_chip_addr()
454 	return (spi_get_chipselect(mem->spi, 0) == 1) ? ispi->chip0_size : 0;  in intel_spi_chip_addr()
457 static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_read_reg()  argument
461 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_read_reg()
462 	size_t nbytes = op->data.nbytes;  in intel_spi_read_reg()
463 	u8 opcode = op->cmd.opcode;  in intel_spi_read_reg()
466 	writel(addr, ispi->base + FADDR);  in intel_spi_read_reg()
468 	if (ispi->swseq_reg)  in intel_spi_read_reg()
477 	return intel_spi_read_block(ispi, op->data.buf.in, nbytes);  in intel_spi_read_reg()
480 static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_write_reg()  argument
484 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_write_reg()
485 	size_t nbytes = op->data.nbytes;  in intel_spi_write_reg()
486 	u8 opcode = op->cmd.opcode;  in intel_spi_write_reg()
501 		if (!ispi->swseq_reg)  in intel_spi_write_reg()
504 		preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
506 			if (ispi->locked)  in intel_spi_write_reg()
507 				return -EINVAL;  in intel_spi_write_reg()
508 			writel(opcode, ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
515 		ispi->atomic_preopcode = opcode;  in intel_spi_write_reg()
528 	writel(addr, ispi->base + FADDR);  in intel_spi_write_reg()
531 	ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes);  in intel_spi_write_reg()
535 	if (ispi->swseq_reg)  in intel_spi_write_reg()
541 static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_read()  argument
545 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_read()
546 	size_t block_size, nbytes = op->data.nbytes;  in intel_spi_read()
547 	void *read_buf = op->data.buf.in;  in intel_spi_read()
555 	if (WARN_ON_ONCE(ispi->atomic_preopcode))  in intel_spi_read()
556 		ispi->atomic_preopcode = 0;  in intel_spi_read()
563 				   round_up(addr + 1, SZ_4K)) - addr;  in intel_spi_read()
565 		writel(addr, ispi->base + FADDR);  in intel_spi_read()
567 		val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_read()
570 		val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;  in intel_spi_read()
573 		writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_read()
579 		status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_read()
581 			ret = -EIO;  in intel_spi_read()
583 			ret = -EACCES;  in intel_spi_read()
586 			dev_err(ispi->dev, "read error: %x: %#x\n", addr, status);  in intel_spi_read()
594 		nbytes -= block_size;  in intel_spi_read()
602 static int intel_spi_write(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_write()  argument
606 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_write()
607 	size_t block_size, nbytes = op->data.nbytes;  in intel_spi_write()
608 	const void *write_buf = op->data.buf.out;  in intel_spi_write()
613 	ispi->atomic_preopcode = 0;  in intel_spi_write()
620 				   round_up(addr + 1, SZ_4K)) - addr;  in intel_spi_write()
622 		writel(addr, ispi->base + FADDR);  in intel_spi_write()
624 		val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_write()
627 		val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;  in intel_spi_write()
632 			dev_err(ispi->dev, "failed to write block\n");  in intel_spi_write()
638 		writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_write()
642 			dev_err(ispi->dev, "timeout\n");  in intel_spi_write()
646 		status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_write()
648 			ret = -EIO;  in intel_spi_write()
650 			ret = -EACCES;  in intel_spi_write()
653 			dev_err(ispi->dev, "write error: %x: %#x\n", addr, status);  in intel_spi_write()
657 		nbytes -= block_size;  in intel_spi_write()
665 static int intel_spi_erase(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_erase()  argument
669 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_erase()
670 	u8 opcode = op->cmd.opcode;  in intel_spi_erase()
674 	writel(addr, ispi->base + FADDR);  in intel_spi_erase()
676 	if (ispi->swseq_erase)  in intel_spi_erase()
681 	ispi->atomic_preopcode = 0;  in intel_spi_erase()
683 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_erase()
687 	val |= iop->replacement_op;  in intel_spi_erase()
688 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_erase()
694 	status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_erase()
696 		return -EIO;  in intel_spi_erase()
698 		return -EACCES;  in intel_spi_erase()
703 static int intel_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)  in intel_spi_adjust_op_size()  argument
705 	op->data.nbytes = clamp_val(op->data.nbytes, 0, INTEL_SPI_FIFO_SZ);  in intel_spi_adjust_op_size()
712 	if (iop->mem_op.cmd.nbytes != op->cmd.nbytes ||  in intel_spi_cmp_mem_op()
713 	    iop->mem_op.cmd.buswidth != op->cmd.buswidth ||  in intel_spi_cmp_mem_op()
714 	    iop->mem_op.cmd.dtr != op->cmd.dtr)  in intel_spi_cmp_mem_op()
717 	if (iop->mem_op.addr.nbytes != op->addr.nbytes ||  in intel_spi_cmp_mem_op()
718 	    iop->mem_op.addr.dtr != op->addr.dtr)  in intel_spi_cmp_mem_op()
721 	if (iop->mem_op.data.dir != op->data.dir ||  in intel_spi_cmp_mem_op()
722 	    iop->mem_op.data.dtr != op->data.dtr)  in intel_spi_cmp_mem_op()
725 	if (iop->mem_op.data.dir != SPI_MEM_NO_DATA) {  in intel_spi_cmp_mem_op()
726 		if (iop->mem_op.data.buswidth != op->data.buswidth)  in intel_spi_cmp_mem_op()
738 	for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) {  in intel_spi_match_mem_op()
739 		if (iop->mem_op.cmd.opcode == op->cmd.opcode &&  in intel_spi_match_mem_op()
747 static bool intel_spi_supports_mem_op(struct spi_mem *mem,  in intel_spi_supports_mem_op()  argument
750 	struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);  in intel_spi_supports_mem_op()
755 		dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);  in intel_spi_supports_mem_op()
763 	if (ispi->swseq_reg && ispi->locked) {  in intel_spi_supports_mem_op()
767 		for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) {  in intel_spi_supports_mem_op()
768 			if (ispi->opcodes[i] == op->cmd.opcode)  in intel_spi_supports_mem_op()
772 		dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);  in intel_spi_supports_mem_op()
779 static int intel_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)  in intel_spi_exec_mem_op()  argument
781 	struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);  in intel_spi_exec_mem_op()
786 		return -EOPNOTSUPP;  in intel_spi_exec_mem_op()
788 	return iop->exec_op(ispi, mem, iop, op);  in intel_spi_exec_mem_op()
791 static const char *intel_spi_get_name(struct spi_mem *mem)  in intel_spi_get_name()  argument
793 	const struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);  in intel_spi_get_name()
799 	return dev_name(ispi->dev);  in intel_spi_get_name()
804 	struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);  in intel_spi_dirmap_create()
807 	iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl);  in intel_spi_dirmap_create()
809 		return -EOPNOTSUPP;  in intel_spi_dirmap_create()
811 	desc->priv = (void *)iop;  in intel_spi_dirmap_create()
818 	struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);  in intel_spi_dirmap_read()
819 	const struct intel_spi_mem_op *iop = desc->priv;  in intel_spi_dirmap_read()
820 	struct spi_mem_op op = desc->info.op_tmpl;  in intel_spi_dirmap_read()
828 	ret = iop->exec_op(ispi, desc->mem, iop, &op);  in intel_spi_dirmap_read()
835 	struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);  in intel_spi_dirmap_write()
836 	const struct intel_spi_mem_op *iop = desc->priv;  in intel_spi_dirmap_write()
837 	struct spi_mem_op op = desc->info.op_tmpl;  in intel_spi_dirmap_write()
844 	ret = iop->exec_op(ispi, desc->mem, iop, &op);  in intel_spi_dirmap_write()
979 	/* Read with 4-byte address opcode */				\
992 	/* Fast read with 4-byte address opcode */			\
1075 	switch (ispi->info->type) {  in intel_spi_init()
1077 		ispi->sregs = ispi->base + BYT_SSFSTS_CTL;  in intel_spi_init()
1078 		ispi->pregs = ispi->base + BYT_PR;  in intel_spi_init()
1079 		ispi->nregions = BYT_FREG_NUM;  in intel_spi_init()
1080 		ispi->pr_num = BYT_PR_NUM;  in intel_spi_init()
1081 		ispi->swseq_reg = true;  in intel_spi_init()
1085 		ispi->sregs = ispi->base + LPT_SSFSTS_CTL;  in intel_spi_init()
1086 		ispi->pregs = ispi->base + LPT_PR;  in intel_spi_init()
1087 		ispi->nregions = LPT_FREG_NUM;  in intel_spi_init()
1088 		ispi->pr_num = LPT_PR_NUM;  in intel_spi_init()
1089 		ispi->swseq_reg = true;  in intel_spi_init()
1093 		ispi->sregs = ispi->base + BXT_SSFSTS_CTL;  in intel_spi_init()
1094 		ispi->pregs = ispi->base + BXT_PR;  in intel_spi_init()
1095 		ispi->nregions = BXT_FREG_NUM;  in intel_spi_init()
1096 		ispi->pr_num = BXT_PR_NUM;  in intel_spi_init()
1101 		ispi->sregs = NULL;  in intel_spi_init()
1102 		ispi->pregs = ispi->base + CNL_PR;  in intel_spi_init()
1103 		ispi->nregions = CNL_FREG_NUM;  in intel_spi_init()
1104 		ispi->pr_num = CNL_PR_NUM;  in intel_spi_init()
1109 		return -EINVAL;  in intel_spi_init()
1114 		dev_warn(ispi->dev, "can't disable chip write protection\n");  in intel_spi_init()
1119 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_init()
1121 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_init()
1131 	lvscc = readl(ispi->base + LVSCC);  in intel_spi_init()
1132 	uvscc = readl(ispi->base + UVSCC);  in intel_spi_init()
1134 		ispi->swseq_erase = true;  in intel_spi_init()
1136 	if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)  in intel_spi_init()
1141 	if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) {  in intel_spi_init()
1142 		dev_err(ispi->dev, "software sequencer not supported, but required\n");  in intel_spi_init()
1143 		return -EINVAL;  in intel_spi_init()
1151 	if (ispi->swseq_reg) {  in intel_spi_init()
1153 		val = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1155 		writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1159 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_init()
1160 	ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);  in intel_spi_init()
1162 	if (ispi->locked && ispi->sregs) {  in intel_spi_init()
1168 		opmenu0 = readl(ispi->sregs + OPMENU0);  in intel_spi_init()
1169 		opmenu1 = readl(ispi->sregs + OPMENU1);  in intel_spi_init()
1172 			for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {  in intel_spi_init()
1173 				ispi->opcodes[i] = opmenu0 >> i * 8;  in intel_spi_init()
1174 				ispi->opcodes[i + 4] = opmenu1 >> i * 8;  in intel_spi_init()
1180 		dev_dbg(ispi->dev, "Using erase_64k memory operations");  in intel_spi_init()
1181 		ispi->mem_ops = erase_64k_mem_ops;  in intel_spi_init()
1183 		dev_dbg(ispi->dev, "Using generic memory operations");  in intel_spi_init()
1184 		ispi->mem_ops = generic_mem_ops;  in intel_spi_init()
1192 				   unsigned int base, unsigned int limit)  in intel_spi_is_protected()  argument
1196 	for (i = 0; i < ispi->pr_num; i++) {  in intel_spi_is_protected()
1199 		pr_value = readl(ispi->pregs + PR(i));  in intel_spi_is_protected()
1206 		if (pr_base >= base && pr_limit <= limit)  in intel_spi_is_protected()
1226 	part->size = 4096;  in intel_spi_fill_partition()
1227 	part->name = "BIOS";  in intel_spi_fill_partition()
1233 	for (i = 1; i < ispi->nregions; i++) {  in intel_spi_fill_partition()
1234 		u32 region, base, limit;  in intel_spi_fill_partition()  local
1236 		region = readl(ispi->base + FREG(i));  in intel_spi_fill_partition()
1237 		base = region & FREG_BASE_MASK;  in intel_spi_fill_partition()
1240 		if (base >= limit || limit == 0)  in intel_spi_fill_partition()
1245 		 * whole partition read-only to be on the safe side.  in intel_spi_fill_partition()
1250 		if (!writeable || intel_spi_is_protected(ispi, base, limit))  in intel_spi_fill_partition()
1251 			part->mask_flags |= MTD_WRITEABLE;  in intel_spi_fill_partition()
1254 		if (end > part->size)  in intel_spi_fill_partition()
1255 			part->size = end;  in intel_spi_fill_partition()
1262 	if (ispi->chip0_size && part->size > ispi->chip0_size)  in intel_spi_fill_partition()
1263 		part->size = MTDPART_SIZ_FULL;  in intel_spi_fill_partition()
1282 		dev_warn(ispi->dev, "failed to read descriptor\n");  in intel_spi_read_desc()
1286 	dev_dbg(ispi->dev, "FLVALSIG=0x%08x\n", buf[0]);  in intel_spi_read_desc()
1287 	dev_dbg(ispi->dev, "FLMAP0=0x%08x\n", buf[1]);  in intel_spi_read_desc()
1290 		dev_warn(ispi->dev, "descriptor signature not valid\n");  in intel_spi_read_desc()
1291 		return -ENODEV;  in intel_spi_read_desc()
1295 	dev_dbg(ispi->dev, "FCBA=%#x\n", fcba);  in intel_spi_read_desc()
1303 		dev_warn(ispi->dev, "failed to read FLCOMP\n");  in intel_spi_read_desc()
1304 		return -ENODEV;  in intel_spi_read_desc()
1307 	dev_dbg(ispi->dev, "FLCOMP=0x%08x\n", flcomp);  in intel_spi_read_desc()
1311 		ispi->chip0_size = SZ_512K;  in intel_spi_read_desc()
1314 		ispi->chip0_size = SZ_1M;  in intel_spi_read_desc()
1317 		ispi->chip0_size = SZ_2M;  in intel_spi_read_desc()
1320 		ispi->chip0_size = SZ_4M;  in intel_spi_read_desc()
1323 		ispi->chip0_size = SZ_8M;  in intel_spi_read_desc()
1326 		ispi->chip0_size = SZ_16M;  in intel_spi_read_desc()
1329 		ispi->chip0_size = SZ_32M;  in intel_spi_read_desc()
1332 		ispi->chip0_size = SZ_64M;  in intel_spi_read_desc()
1335 		return -EINVAL;  in intel_spi_read_desc()
1338 	dev_dbg(ispi->dev, "chip0 size %zd KB\n", ispi->chip0_size / SZ_1K);  in intel_spi_read_desc()
1342 		ispi->host->num_chipselect = 1;  in intel_spi_read_desc()
1344 		ispi->host->num_chipselect = 2;  in intel_spi_read_desc()
1346 		return -EINVAL;  in intel_spi_read_desc()
1348 	dev_dbg(ispi->dev, "%u flash components found\n",  in intel_spi_read_desc()
1349 		ispi->host->num_chipselect);  in intel_spi_read_desc()
1364 	pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL);  in intel_spi_populate_chip()
1366 		return -ENOMEM;  in intel_spi_populate_chip()
1368 	pdata->nr_parts = 1;  in intel_spi_populate_chip()
1369 	pdata->parts = devm_kcalloc(ispi->dev, pdata->nr_parts,  in intel_spi_populate_chip()
1370 				    sizeof(*pdata->parts), GFP_KERNEL);  in intel_spi_populate_chip()
1371 	if (!pdata->parts)  in intel_spi_populate_chip()
1372 		return -ENOMEM;  in intel_spi_populate_chip()
1374 	intel_spi_fill_partition(ispi, pdata->parts);  in intel_spi_populate_chip()
1377 	snprintf(chip.modalias, 8, "spi-nor");  in intel_spi_populate_chip()
1380 	if (!spi_new_device(ispi->host, &chip))  in intel_spi_populate_chip()
1381 		return -ENODEV;  in intel_spi_populate_chip()
1384 	if (ispi->host->num_chipselect < 2)  in intel_spi_populate_chip()
1387 	pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL);  in intel_spi_populate_chip()
1389 		return -ENOMEM;  in intel_spi_populate_chip()
1391 	pdata->name = devm_kasprintf(ispi->dev, GFP_KERNEL, "%s-chip1",  in intel_spi_populate_chip()
1392 				     dev_name(ispi->dev));  in intel_spi_populate_chip()
1393 	if (!pdata->name)  in intel_spi_populate_chip()
1394 		return -ENOMEM;  in intel_spi_populate_chip()
1396 	pdata->nr_parts = 1;  in intel_spi_populate_chip()
1397 	parts = devm_kcalloc(ispi->dev, pdata->nr_parts, sizeof(*parts),  in intel_spi_populate_chip()
1400 		return -ENOMEM;  in intel_spi_populate_chip()
1404 	pdata->parts = parts;  in intel_spi_populate_chip()
1409 	if (!spi_new_device(ispi->host, &chip))  in intel_spi_populate_chip()
1410 		return -ENODEV;  in intel_spi_populate_chip()
1415  * intel_spi_probe() - Probe the Intel SPI flash controller
1417  * @mem: MMIO resource
1423 int intel_spi_probe(struct device *dev, struct resource *mem,  in intel_spi_probe()  argument
1432 		return -ENOMEM;  in intel_spi_probe()
1434 	host->mem_ops = &intel_spi_mem_ops;  in intel_spi_probe()
1438 	ispi->base = devm_ioremap_resource(dev, mem);  in intel_spi_probe()
1439 	if (IS_ERR(ispi->base))  in intel_spi_probe()
1440 		return PTR_ERR(ispi->base);  in intel_spi_probe()
1442 	ispi->dev = dev;  in intel_spi_probe()
1443 	ispi->host = host;  in intel_spi_probe()
1444 	ispi->info = info;  in intel_spi_probe()