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/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
26 interrupt configuration registers, and have a rx and tx interrupt source per
28 appropriate programming of the rx and tx interrupt sources on the appropriate
35 lines can also be routed to different processor sub-systems on DRA7xx as they
49 within a SoC. The sub-mailboxes (actual communication channels) are
56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
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H A Dhisilicon,hi6220-mailbox.txt13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
23 slot_id: Slot id used either for TX or RX
26 TX/RX interrupt to application processor,
28 - interrupts: Contains the interrupt information for the mailbox
33 --------------------
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
36 flag" mode or IRQ generated mode to acknowledge a TX
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/linux/drivers/firmware/tegra/
H A Dbpmp-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <soc/tegra/bpmp-abi.h>
16 #include "bpmp-private.h"
28 } tx, rx; member
33 } mbox; member
41 priv = container_of(client, struct tegra186_bpmp, mbox.client); in mbox_client_to_bpmp()
43 return priv->parent; in mbox_client_to_bpmp()
50 err = tegra_ivc_read_get_next_frame(channel->ivc, &channel->ib); in tegra186_bpmp_is_message_ready()
52 iosys_map_clear(&channel->ib); in tegra186_bpmp_is_message_ready()
63 err = tegra_ivc_write_get_next_frame(channel->ivc, &channel->ob); in tegra186_bpmp_is_channel_free()
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/linux/drivers/mailbox/
H A Dmailbox.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 Linaro Ltd.
32 spin_lock_irqsave(&chan->lock, flags); in add_to_rbuf()
35 if (chan->msg_count == MBOX_TX_QUEUE_LEN) { in add_to_rbuf()
36 spin_unlock_irqrestore(&chan->lock, flags); in add_to_rbuf()
37 return -ENOBUFS; in add_to_rbuf()
40 idx = chan->msg_free; in add_to_rbuf()
41 chan->msg_data[idx] = mssg; in add_to_rbuf()
42 chan->msg_count++; in add_to_rbuf()
44 if (idx == MBOX_TX_QUEUE_LEN - 1) in add_to_rbuf()
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H A Dmailbox-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #define STI_IRQ_SET_OFFSET 0x24 /* Generate a Tx channel interrupt */
36 #define MBOX_BASE(mdev, inst) ((mdev)->base + ((inst) * 4))
39 * struct sti_mbox_device - STi Mailbox device data
42 * @mbox: Representation of a communication channel controller
51 * A channel an be used for TX or RX
55 struct mbox_controller *mbox; member
63 * struct sti_mbox_pdata - STi Mailbox platform specific configuration
74 * struct sti_channel - STi Mailbox allocated channel information
88 struct sti_channel *chan_info = chan->con_priv; in sti_mbox_channel_is_enabled()
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H A Dhi6220-mailbox.c1 // SPDX-License-Identifier: GPL-2.0-only
57 * - direction: tx or rx
58 * - dst irq: peer core's irq number
59 * - ack irq: local irq number
60 * - slot number
73 /* flag of enabling tx's irq mode */
90 static void mbox_set_state(struct hi6220_mbox *mbox, in mbox_set_state() argument
95 status = readl(mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
97 writel(status, mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
100 static void mbox_set_mode(struct hi6220_mbox *mbox, in mbox_set_mode() argument
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H A Dimx-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
29 /* TX0/RX0/RXDB[0-3] */
42 /* Please not change TX & RX */
44 IMX_MU_TYPE_TX = 0, /* Tx */
46 IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */
49 IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */
93 struct mbox_controller mbox; member
116 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); member
127 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
128 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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H A Domap-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
6 * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com
9 * Suman Anna <s-anna@ti.com>
97 return __raw_readl(mdev->mbox_base + ofs); in mbox_read_reg()
103 __raw_writel(val, mdev->mbox_base + ofs); in mbox_write_reg()
107 static u32 mbox_fifo_read(struct omap_mbox *mbox) in mbox_fifo_read() argument
109 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_read()
111 return mbox_read_reg(mbox->parent, fifo->msg); in mbox_fifo_read()
114 static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg) in mbox_fifo_write() argument
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H A Darm_mhuv2.c1 // SPDX-License-Identifier: GPL-2.0
10 * protocol modes: data-transfer and doorbell, to be used on those channel
19 * hardware - mainly the number of channel windows implemented by the platform,
45 #define LSB_MASK(n) ((1 << (n * __CHAR_BIT__)) - 1)
46 #define MHUV2_PROTOCOL_PROP "arm,mhuv2-protocols"
94 u8 pad1[0x0C - 0x04];
99 u8 pad2[0x20 - 0x1C];
114 u8 pad[0xFC8 - 0xFB0];
124 u8 reserved0[0x10 - 0x0C];
128 u8 pad[0x20 - 0x1C];
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H A Dqcom-cpucp-mbox.c1 // SPDX-License-Identifier: GPL-2.0-only
18 /* Tx Registers */
30 * struct qcom_cpucp_mbox - Holder for the mailbox driver
32 * @mbox: The mailbox controller
33 * @tx_base: Base address of the CPUCP tx registers
38 struct mbox_controller mbox; member
45 return chan - chan->mbox->chans; in channel_number()
54 status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); in qcom_cpucp_mbox_irq_fn()
57 u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); in qcom_cpucp_mbox_irq_fn()
58 struct mbox_chan *chan = &cpucp->chans[i]; in qcom_cpucp_mbox_irq_fn()
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H A Dzynqmp-ipi-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/arm-smccc.h>
17 #include <linux/mailbox/zynqmp-ipi-message.h>
55 #define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
75 * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
99 * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
105 * @mbox: mailbox Controller
106 * @mchans: array for channels, tx channel and rx channel.
113 struct mbox_controller mbox; member
119 * struct zynqmp_ipi_pdata - Description of z ZynqMP IPI agent platform data.
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am68-sk-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j721s2.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
14 bootph-all;
20 reserved_memory: reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
27 no-map;
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H A Dk3-am642-tqma64xxl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
7 #include "k3-am642.dtsi"
18 /* 1G RAM - default variant */
23 reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
31 no-map;
34 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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H A Dk3-j721e-som-p0.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
15 bootph-all;
21 reserved_memory: reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
29 no-map;
32 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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H A Dk3-j721s2-som-p0.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721s2.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
16 bootph-all;
23 reserved_memory: reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
31 no-map;
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H A Dk3-am64-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
6 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
10 * https://www.phytec.com/product/phycore-am64x
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/net/ti-dp83867.h>
18 model = "PHYTEC phyCORE-AM64x";
19 compatible = "phytec,am64-phycore-som", "ti,am642";
32 reserved_memory: reserved-memory {
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H A Dk3-am69-sk.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include "k3-j784s4.dtsi"
16 compatible = "ti,am69-sk", "ti,j784s4";
20 stdout-path = "serial2:115200n8";
36 bootph-all;
42 reserved_memory: reserved-memory {
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/linux/arch/arm/boot/dts/ti/omap/
H A Domap2420.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,omap2-l4", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
21 compatible = "ti,omap2-prcm";
25 #address-cells = <1>;
26 #size-cells = <0>;
34 compatible = "ti,omap2-scm", "simple-bus";
36 #address-cells = <1>;
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H A Ddra72x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
20 compatible = "arm,cortex-a15-pmu";
21 interrupt-parent = <&wakeupgen>;
27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
28 compatible = "ti,sysc-omap4", "ti,sysc";
31 reg-names = "rev", "sysc";
32 ti,sysc-midle = <SYSC_IDLE_FORCE>,
34 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
37 clock-names = "fck";
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H A Ddra74x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
16 compatible = "arm,cortex-a15";
18 operating-points-v2 = <&cpu0_opp_table>;
21 clock-names = "cpu";
23 clock-latency = <300000>; /* From omap-cpufreq driver */
26 #cooling-cells = <2>; /* min followed by max */
28 vbb-supply = <&abb_mpu>;
40 compatible = "arm,cortex-a15-pmu";
41 interrupt-parent = <&wakeupgen>;
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H A Domap2430.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,omap2-l4-wkup", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
21 compatible = "ti,omap2-prcm";
25 #address-cells = <1>;
26 #size-cells = <0>;
34 compatible = "ti,omap2-scm", "simple-bus";
36 #address-cells = <1>;
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/linux/include/linux/
H A Dmailbox_controller.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 * struct mbox_chan_ops - methods to control mailbox channels
16 * @send_data: The API asks the MBOX controller driver, in atomic
18 * data is accepted for transmission, -EBUSY while rejecting
21 * mbox_chan_txdone (if it has some TX ACK irq). It must not
37 * this to poll status of last TX. The controller must
40 * mode 'send_data' is expected to return -EBUSY.
56 * struct mbox_controller - Controller of a class of communication channels
63 * Eg, if it has some TX ACK irq.
64 * @txdone_poll: If the controller can read but not report the TX
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/linux/Documentation/devicetree/bindings/firmware/
H A Darm,scmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
26 - $ref: /schemas/firmware/nxp,imx95-scmi.yaml
34 - description: SCMI compliant firmware with mailbox transport
36 - const: arm,scmi
37 - description: SCMI compliant firmware with ARM SMC/HVC transport
39 - const: arm,scmi-smc
40 - description: SCMI compliant firmware with ARM SMC/HVC transport
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/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4.h4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
62 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
67 /* Suspend an Ethernet Tx queue with fewer available descriptors than this.
138 FEC_RS = 1 << 1, /* Reed-Solomon */
139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
213 u64 tx_frames_64; /* # of Tx frames in a particular range */
221 u64 tx_drop; /* # of dropped Tx frames */
262 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
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/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_cn9k.c1 // SPDX-License-Identifier: GPL-2.0
19 struct device *dev = &oct->pdev->dev; in cn93_vf_dump_q_regs()
21 dev_info(dev, "IQ-%d register dump\n", qno); in cn93_vf_dump_q_regs()
50 dev_info(dev, "OQ-%d register dump\n", qno); in cn93_vf_dump_q_regs()
80 /* Reset Hardware Tx queue */
85 dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no); in cn93_vf_reset_iq()
87 /* Disable the Tx/Instruction Ring */ in cn93_vf_reset_iq()
121 /* Reset all hardware Tx/Rx queues */
124 struct pci_dev *pdev = oct->pdev; in octep_vf_reset_io_queues_cn93()
127 dev_dbg(&pdev->dev, "Reset OCTEP_CN93 VF IO Queues\n"); in octep_vf_reset_io_queues_cn93()
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