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/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
26 interrupt configuration registers, and have a rx and tx interrupt source per
28 appropriate programming of the rx and tx interrupt sources on the appropriate
35 lines can also be routed to different processor sub-systems on DRA7xx as they
49 within a SoC. The sub-mailboxes (actual communication channels) are
56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
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H A Dhisilicon,hi6220-mailbox.txt13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
23 slot_id: Slot id used either for TX or RX
26 TX/RX interrupt to application processor,
28 - interrupts: Contains the interrupt information for the mailbox
33 --------------------
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
36 flag" mode or IRQ generated mode to acknowledge a TX
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H A Dbrcm,bcm74110-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/brcm,bcm74110-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Justin Chen <justin.chen@broadcom.com>
11 - Florian Fainelli <florian.fainelli@broadcom.com>
18 - brcm,bcm74110-mbox
25 - description: RX doorbell and watermark interrupts
26 - description: TX doorbell and watermark interrupts
28 "#mbox-cells":
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H A Dcix,sky1-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/cix,sky1-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guomin Chen <Guomin.Chen@cixtech.com>
19 typically used in pairs-one for receiving and one for transmitting.
22 channel 0-7 - Fast channel with 32bit transmit register and IRQ support
23 channel 8 - Doorbell mode,using the mailbox as an interrupt-generating
25 channel 9 - Fifo based channel with 32*32bit depth fifo and IRQ support
26 channel 10 - Reg based channel with 32*32bit transmit register and
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H A Daspeed,ast2700-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/aspeed,ast2700-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jammy Huang <jammy_huang@aspeedtech.com>
15 messages to each other. It is a hardware-based inter-processor communication
19 The mailbox's tx/rx are independent, meaning that one processor can send a
21 There are 4 channels available for both tx and rx operations. Each channel
31 const: aspeed,ast2700-mailbox
35 - description: TX control register
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H A Dst,stm32-ipcc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Fabien Dessenne <fabien.dessenne@foss.st.com>
17 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
21 const: st,stm32mp1-ipcc
31 - description: rx channel occupied
32 - description: tx channel free
34 interrupt-names:
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/linux/drivers/firmware/tegra/
H A Dbpmp-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <soc/tegra/bpmp-abi.h>
16 #include "bpmp-private.h"
28 } tx, rx; member
33 } mbox; member
41 priv = container_of(client, struct tegra186_bpmp, mbox.client); in mbox_client_to_bpmp()
43 return priv->parent; in mbox_client_to_bpmp()
50 err = tegra_ivc_read_get_next_frame(channel->ivc, &channel->ib); in tegra186_bpmp_is_message_ready()
52 iosys_map_clear(&channel->ib); in tegra186_bpmp_is_message_ready()
63 err = tegra_ivc_write_get_next_frame(channel->ivc, &channel->ob); in tegra186_bpmp_is_channel_free()
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/linux/drivers/mailbox/
H A Dbcm74110-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/io-64-nonatomic-hi-lo.h>
94 struct bcm74110_mbox *mbox; member
115 static void bcm74110_##name##_writel(struct bcm74110_mbox *mbox,\
118 writel_relaxed(val, mbox->base + offset_base + off); \
120 BCM74110_OFFSET_IO_WRITEL_MACRO(tx, BCM_MBOX_BASE(mbox->tx_chan));
121 BCM74110_OFFSET_IO_WRITEL_MACRO(irq, BCM_MBOX_IRQ_BASE(mbox->rx_chan));
124 static u32 bcm74110_##name##_readl(struct bcm74110_mbox *mbox, \
127 return readl_relaxed(mbox->base + offset_base + off); \
129 BCM74110_OFFSET_IO_READL_MACRO(tx, BCM_MBOX_BASE(mbox->tx_chan));
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H A Dmailbox-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #define STI_IRQ_SET_OFFSET 0x24 /* Generate a Tx channel interrupt */
36 #define MBOX_BASE(mdev, inst) ((mdev)->base + ((inst) * 4))
39 * struct sti_mbox_device - STi Mailbox device data
42 * @mbox: Representation of a communication channel controller
51 * A channel an be used for TX or RX
55 struct mbox_controller *mbox; member
63 * struct sti_mbox_pdata - STi Mailbox platform specific configuration
74 * struct sti_channel - STi Mailbox allocated channel information
88 struct sti_channel *chan_info = chan->con_priv; in sti_mbox_channel_is_enabled()
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H A Dhi6220-mailbox.c1 // SPDX-License-Identifier: GPL-2.0-only
57 * - direction: tx or rx
58 * - dst irq: peer core's irq number
59 * - ack irq: local irq number
60 * - slot number
73 /* flag of enabling tx's irq mode */
90 static void mbox_set_state(struct hi6220_mbox *mbox, in mbox_set_state() argument
95 status = readl(mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
97 writel(status, mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
100 static void mbox_set_mode(struct hi6220_mbox *mbox, in mbox_set_mode() argument
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H A Domap-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
6 * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com
9 * Suman Anna <s-anna@ti.com>
97 return __raw_readl(mdev->mbox_base + ofs); in mbox_read_reg()
103 __raw_writel(val, mdev->mbox_base + ofs); in mbox_write_reg()
107 static u32 mbox_fifo_read(struct omap_mbox *mbox) in mbox_fifo_read() argument
109 struct omap_mbox_fifo *fifo = &mbox->rx_fifo; in mbox_fifo_read()
111 return mbox_read_reg(mbox->parent, fifo->msg); in mbox_fifo_read()
114 static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg) in mbox_fifo_write() argument
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H A Dqcom-cpucp-mbox.c1 // SPDX-License-Identifier: GPL-2.0-only
18 /* Tx Registers */
30 * struct qcom_cpucp_mbox - Holder for the mailbox driver
32 * @mbox: The mailbox controller
33 * @tx_base: Base address of the CPUCP tx registers
38 struct mbox_controller mbox; member
45 return chan - chan->mbox->chans; in channel_number()
54 status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); in qcom_cpucp_mbox_irq_fn()
57 u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); in qcom_cpucp_mbox_irq_fn()
58 struct mbox_chan *chan = &cpucp->chans[i]; in qcom_cpucp_mbox_irq_fn()
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H A Dcix-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
98 struct mbox_controller mbox; member
112 static struct cix_mbox_priv *to_cix_mbox_priv(struct mbox_controller *mbox) in to_cix_mbox_priv() argument
114 return container_of(mbox, struct cix_mbox_priv, mbox); in to_cix_mbox_priv()
119 if (priv->use_shmem) in cix_mbox_write()
120 iowrite32(val, priv->base + offset - CIX_SHMEM_OFFSET); in cix_mbox_write()
122 iowrite32(val, priv->base + offset); in cix_mbox_write()
127 if (priv->use_shmem) in cix_mbox_read()
128 return ioread32(priv->base + offset - CIX_SHMEM_OFFSET); in cix_mbox_read()
130 return ioread32(priv->base + offset); in cix_mbox_read()
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H A Dti-msgmgr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/
22 #include <linux/soc/ti/ti-msgmgr.h>
41 * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
53 * struct ti_msgmgr_desc - Description of message manager integration
61 * @tx_polled: Do I need to use polled mechanism for tx
92 * struct ti_queue_inst - Description of a queue instance
122 * struct ti_msgmgr_inst - Description of a Message Manager Instance
132 * @mbox: Mailbox Controller
143 struct mbox_controller mbox; member
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/linux/arch/arm/boot/dts/ti/omap/
H A Domap2420.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,omap2-l4", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
21 compatible = "ti,omap2-prcm";
25 #address-cells = <1>;
26 #size-cells = <0>;
34 compatible = "ti,omap2-scm", "simple-bus";
36 #address-cells = <1>;
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H A Ddra72x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
20 compatible = "arm,cortex-a15-pmu";
21 interrupt-parent = <&wakeupgen>;
27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
28 compatible = "ti,sysc-omap4", "ti,sysc";
31 reg-names = "rev", "sysc";
32 ti,sysc-midle = <SYSC_IDLE_FORCE>,
34 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
37 clock-names = "fck";
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H A Ddra74x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
16 compatible = "arm,cortex-a15";
18 operating-points-v2 = <&cpu0_opp_table>;
21 clock-names = "cpu";
23 clock-latency = <300000>; /* From omap-cpufreq driver */
26 #cooling-cells = <2>; /* min followed by max */
28 vbb-supply = <&abb_mpu>;
40 compatible = "arm,cortex-a15-pmu";
41 interrupt-parent = <&wakeupgen>;
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H A Domap2430.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,omap2-l4-wkup", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
21 compatible = "ti,omap2-prcm";
25 #address-cells = <1>;
26 #size-cells = <0>;
34 compatible = "ti,omap2-scm", "simple-bus";
36 #address-cells = <1>;
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/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4.h4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
62 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
67 /* Suspend an Ethernet Tx queue with fewer available descriptors than this.
138 FEC_RS = 1 << 1, /* Reed-Solomon */
139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
213 u64 tx_frames_64; /* # of Tx frames in a particular range */
221 u64 tx_drop; /* # of dropped Tx frames */
262 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
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/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_cn9k.c1 // SPDX-License-Identifier: GPL-2.0
19 struct device *dev = &oct->pdev->dev; in cn93_vf_dump_q_regs()
21 dev_info(dev, "IQ-%d register dump\n", qno); in cn93_vf_dump_q_regs()
50 dev_info(dev, "OQ-%d register dump\n", qno); in cn93_vf_dump_q_regs()
80 /* Reset Hardware Tx queue */
85 dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no); in cn93_vf_reset_iq()
87 /* Disable the Tx/Instruction Ring */ in cn93_vf_reset_iq()
121 /* Reset all hardware Tx/Rx queues */
124 struct pci_dev *pdev = oct->pdev; in octep_vf_reset_io_queues_cn93()
127 dev_dbg(&pdev->dev, "Reset OCTEP_CN93 VF IO Queues\n"); in octep_vf_reset_io_queues_cn93()
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H A Doctep_vf_cnxk.c1 // SPDX-License-Identifier: GPL-2.0
19 struct device *dev = &oct->pdev->dev; in cnxk_vf_dump_q_regs()
21 dev_info(dev, "IQ-%d register dump\n", qno); in cnxk_vf_dump_q_regs()
50 dev_info(dev, "OQ-%d register dump\n", qno); in cnxk_vf_dump_q_regs()
83 /* Reset Hardware Tx queue */
88 dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no); in cnxk_vf_reset_iq()
90 /* Disable the Tx/Instruction Ring */ in cnxk_vf_reset_iq()
123 /* Reset all hardware Tx/Rx queues */
126 struct pci_dev *pdev = oct->pdev; in octep_vf_reset_io_queues_cnxk()
129 dev_dbg(&pdev->dev, "Reset OCTEP_CNXK VF IO Queues\n"); in octep_vf_reset_io_queues_cnxk()
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/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dmbox.h1 /* SPDX-License-Identifier: GPL-2.0 */
39 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
41 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */
43 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
61 void *mbase; /* This dev's mbox region */
72 void *hwbase; /* Mbox region advertised by HW */
74 u64 trigger; /* Trigger mbox notification */
75 u16 tr_shift; /* Mbox trigger shift */
76 u64 rx_start; /* Offset of Rx region in mbox memory */
77 u64 tx_start; /* Offset of Tx region in mbox memory */
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/linux/drivers/net/wireless/ti/wl12xx/
H A Devent.c1 // SPDX-License-Identifier: GPL-2.0-only
36 struct wl12xx_event_mailbox *mbox = wl->mbox; in wl12xx_process_mailbox_events() local
40 vector = le32_to_cpu(mbox->events_vector); in wl12xx_process_mailbox_events()
41 vector &= ~(le32_to_cpu(mbox->events_mask)); in wl12xx_process_mailbox_events()
43 wl1271_debug(DEBUG_EVENT, "MBOX vector: 0x%x", vector); in wl12xx_process_mailbox_events()
47 mbox->scheduled_scan_status); in wl12xx_process_mailbox_events()
49 if (wl->scan_wlvif) in wl12xx_process_mailbox_events()
50 wl12xx_scan_completed(wl, wl->scan_wlvif); in wl12xx_process_mailbox_events()
56 mbox->scheduled_scan_status); in wl12xx_process_mailbox_events()
63 mbox->scheduled_scan_status); in wl12xx_process_mailbox_events()
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/linux/Documentation/devicetree/bindings/dsp/
H A Dfsl,dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Baluta <daniel.baluta@nxp.com>
11 - Shengjiu Wang <shengjiu.wang@nxp.com>
15 advanced pre- and post- audio processing.
20 - fsl,imx8qxp-dsp
21 - fsl,imx8qm-dsp
22 - fsl,imx8mp-dsp
23 - fsl,imx8ulp-dsp
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/linux/Documentation/devicetree/bindings/arm/keystone/
H A Dti,sci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
29 relationship between the TI-SCI parent node to the child node.
33 pattern: "^system-controller@[0-9a-f]+$"
37 - description: System controller on TI 66AK2G SoC and other K3 SoCs
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