/linux/Documentation/devicetree/bindings/mailbox/ |
H A D | ti,omap-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Suman Anna <s-anna@ti.com> 26 interrupt configuration registers, and have a rx and tx interrupt source per 28 appropriate programming of the rx and tx interrupt sources on the appropriate 35 lines can also be routed to different processor sub-systems on DRA7xx as they 49 within a SoC. The sub-mailboxes (actual communication channels) are 56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt [all …]
|
H A D | hisilicon,hi6220-mailbox.txt | 13 -------------------- 14 - compatible: Shall be "hisilicon,hi6220-mbox" 15 - reg: Contains the mailbox register address range (base 19 - #mbox-cells: Common mailbox binding property to identify the number 23 slot_id: Slot id used either for TX or RX 26 TX/RX interrupt to application processor, 28 - interrupts: Contains the interrupt information for the mailbox 33 -------------------- 34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver 40 -------- [all …]
|
H A D | brcm,iproc-pdc-mbox.txt | 7 - compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for 9 - reg: Should contain PDC registers location and length. 10 - interrupts: Should contain the IRQ line for the PDC. 11 - #mbox-cells: 1 12 - brcm,rx-status-len: Length of metadata preceding received frames, in bytes. 15 - brcm,use-bcm-hdr: present if a BCM header precedes each frame. 18 pdc0: iproc-pdc0@612c0000 { 19 compatible = "brcm,iproc-pdc-mbox"; 22 #mbox-cells = <1>; /* one cell per mailbox channel */ 23 brcm,rx-status-len = <32>; [all …]
|
/linux/drivers/media/platform/amphion/ |
H A D | vpu_mbox.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright 2020-2021 NXP 19 struct vpu_mbox *rx = container_of(cl, struct vpu_mbox, cl); in vpu_mbox_rx_callback() local 20 struct vpu_core *core = container_of(rx, struct vpu_core, rx); in vpu_mbox_rx_callback() 25 static int vpu_mbox_request_channel(struct device *dev, struct vpu_mbox *mbox) in vpu_mbox_request_channel() argument 30 if (!dev || !mbox) in vpu_mbox_request_channel() 31 return -EINVAL; in vpu_mbox_request_channel() 32 if (mbox->ch) in vpu_mbox_request_channel() 35 cl = &mbox->cl; in vpu_mbox_request_channel() 36 cl->dev = dev; in vpu_mbox_request_channel() [all …]
|
/linux/drivers/firmware/tegra/ |
H A D | bpmp-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0 13 #include <soc/tegra/bpmp-abi.h> 16 #include "bpmp-private.h" 28 } tx, rx; member 33 } mbox; member 41 priv = container_of(client, struct tegra186_bpmp, mbox.client); in mbox_client_to_bpmp() 43 return priv->parent; in mbox_client_to_bpmp() 50 err = tegra_ivc_read_get_next_frame(channel->ivc, &channel->ib); in tegra186_bpmp_is_message_ready() 52 iosys_map_clear(&channel->ib); in tegra186_bpmp_is_message_ready() 63 err = tegra_ivc_write_get_next_frame(channel->ivc, &channel->ob); in tegra186_bpmp_is_channel_free() [all …]
|
/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-am68-sk-som.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 /dts-v1/; 8 #include "k3-j721s2.dtsi" 9 #include <dt-bindings/gpio/gpio.h> 14 bootph-all; 20 reserved_memory: reserved-memory { 21 #address-cells = <2>; 22 #size-cells = <2>; 27 no-map; [all …]
|
H A D | k3-am642-tqma64xxl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. 7 #include "k3-am642.dtsi" 18 /* 1G RAM - default variant */ 23 reserved-memory { 24 #address-cells = <2>; 25 #size-cells = <2>; 31 no-map; 34 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { [all …]
|
H A D | k3-j721e-som-p0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 3 * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 /dts-v1/; 10 #include "k3-j721e.dtsi" 15 bootph-all; 21 reserved_memory: reserved-memory { 22 #address-cells = <2>; 23 #size-cells = <2>; 29 no-map; 32 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { [all …]
|
H A D | k3-j721s2-som-p0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 /dts-v1/; 10 #include "k3-j721s2.dtsi" 11 #include <dt-bindings/gpio/gpio.h> 16 bootph-all; 23 reserved_memory: reserved-memory { 24 #address-cells = <2>; 25 #size-cells = <2>; 31 no-map; [all …]
|
H A D | k3-am64-phycore-som.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 3 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com 6 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH 10 * https://www.phytec.com/product/phycore-am64x 13 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/leds/common.h> 15 #include <dt-bindings/net/ti-dp83867.h> 18 model = "PHYTEC phyCORE-AM64x"; 19 compatible = "phytec,am64-phycore-som", "ti,am642"; 32 reserved_memory: reserved-memory { [all …]
|
H A D | k3-am69-sk.dts | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 9 /dts-v1/; 11 #include <dt-bindings/net/ti-dp83867.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include "k3-j784s4.dtsi" 16 compatible = "ti,am69-sk", "ti,j784s4"; 20 stdout-path = "serial2:115200n8"; 36 bootph-all; 42 reserved_memory: reserved-memory { [all …]
|
H A D | k3-j721e-beagleboneai64.dts | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 3 * https://beagleboard.org/ai-64 4 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 5 * Copyright (C) 2022-2024 Jason Kridner, BeagleBoard.org Foundation 6 * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation 9 /dts-v1/; 11 #include "k3-j721e.dtsi" 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/input/input.h> 14 #include <dt-bindings/leds/common.h> [all …]
|
/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap2420.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 15 compatible = "ti,omap2-l4", "simple-bus"; 16 #address-cells = <1>; 17 #size-cells = <1>; 21 compatible = "ti,omap2-prcm"; 25 #address-cells = <1>; 26 #size-cells = <0>; 34 compatible = "ti,omap2-scm", "simple-bus"; 36 #address-cells = <1>; [all …]
|
H A D | dra72x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ 20 compatible = "arm,cortex-a15-pmu"; 21 interrupt-parent = <&wakeupgen>; 27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ 28 compatible = "ti,sysc-omap4", "ti,sysc"; 31 reg-names = "rev", "sysc"; 32 ti,sysc-midle = <SYSC_IDLE_FORCE>, 34 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 37 clock-names = "fck"; [all …]
|
H A D | dra74x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ 16 compatible = "arm,cortex-a15"; 18 operating-points-v2 = <&cpu0_opp_table>; 21 clock-names = "cpu"; 23 clock-latency = <300000>; /* From omap-cpufreq driver */ 26 #cooling-cells = <2>; /* min followed by max */ 28 vbb-supply = <&abb_mpu>; 40 compatible = "arm,cortex-a15-pmu"; 41 interrupt-parent = <&wakeupgen>; [all …]
|
H A D | omap2430.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 15 compatible = "ti,omap2-l4-wkup", "simple-bus"; 16 #address-cells = <1>; 17 #size-cells = <1>; 21 compatible = "ti,omap2-prcm"; 25 #address-cells = <1>; 26 #size-cells = <0>; 34 compatible = "ti,omap2-scm", "simple-bus"; 36 #address-cells = <1>; [all …]
|
/linux/Documentation/devicetree/bindings/media/ |
H A D | amphion,vpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Ming Qian <ming.qian@nxp.com> 12 - Shijie Qin <shijie.qin@nxp.com> 14 description: |- 20 pattern: "^vpu@[0-9a-f]+$" 24 - enum: 25 - nxp,imx8qm-vpu 26 - nxp,imx8qxp-vpu [all …]
|
/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8-ss-vpu.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 8 #address-cells = <1>; 9 #size-cells = <1>; 12 power-domains = <&pd IMX_SC_R_VPU>; 16 compatible = "fsl,imx6sx-mu"; 19 #mbox-cells = <2>; 20 power-domains = <&pd IMX_SC_R_VPU_MU_0>; 25 compatible = "fsl,imx6sx-mu"; 28 #mbox-cells = <2>; 29 power-domains = <&pd IMX_SC_R_VPU_MU_1>; [all …]
|
/linux/drivers/mailbox/ |
H A D | imx-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0 29 /* TX0/RX0/RXDB[0-3] */ 42 /* Please not change TX & RX */ 45 IMX_MU_TYPE_RX = 1, /* Rx */ 47 IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */ 93 struct mbox_controller mbox; member 117 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); member 127 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x)))) 128 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 129 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x)))) [all …]
|
H A D | zynqmp-ipi-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <linux/arm-smccc.h> 17 #include <linux/mailbox/zynqmp-ipi-message.h> 56 #define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */ 75 * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel 99 * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox 105 * @mbox: mailbox Controller 106 * @mchans: array for channels, tx channel and rx channel. 113 struct mbox_controller mbox; member 119 * struct zynqmp_ipi_pdata - Description of z ZynqMP IPI agent platform data. [all …]
|
H A D | ti-msgmgr.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/ 22 #include <linux/soc/ti/ti-msgmgr.h> 41 * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor 53 * struct ti_msgmgr_desc - Description of message manager integration 92 * struct ti_queue_inst - Description of a queue instance 96 * @irq: IRQ for Rx Queue 104 * @polled_rx_mode: Use polling for rx instead of interrupts 122 * struct ti_msgmgr_inst - Description of a Message Manager Instance 132 * @mbox: Mailbox Controller [all …]
|
H A D | qcom-cpucp-mbox.c | 1 // SPDX-License-Identifier: GPL-2.0-only 21 /* Rx Registers */ 30 * struct qcom_cpucp_mbox - Holder for the mailbox driver 32 * @mbox: The mailbox controller 34 * @rx_base: Base address of the CPUCP rx registers 38 struct mbox_controller mbox; member 45 return chan - chan->mbox->chans; in channel_number() 54 status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); in qcom_cpucp_mbox_irq_fn() 57 u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); in qcom_cpucp_mbox_irq_fn() 58 struct mbox_chan *chan = &cpucp->chans[i]; in qcom_cpucp_mbox_irq_fn() [all …]
|
/linux/drivers/net/ethernet/marvell/octeontx2/af/ |
H A D | mbox.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 39 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 54 void *mbase; /* This dev's mbox region */ 65 void *hwbase; /* Mbox region advertised by HW */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ [all …]
|
/linux/drivers/net/wireless/ti/wl18xx/ |
H A D | event.c | 1 // SPDX-License-Identifier: GPL-2.0-only 67 skb = cfg80211_vendor_event_alloc(wl->hw->wiphy, NULL, 20, in wlcore_smart_config_sync_event() 73 return -EMSGSIZE; in wlcore_smart_config_sync_event() 88 skb = cfg80211_vendor_event_alloc(wl->hw->wiphy, NULL, in wlcore_smart_config_decode_event() 96 return -EMSGSIZE; in wlcore_smart_config_decode_event() 118 struct wl18xx_event_mailbox *mbox = wl->mbox; in wl18xx_process_mailbox_events() local 121 vector = le32_to_cpu(mbox->events_vector); in wl18xx_process_mailbox_events() 122 wl1271_debug(DEBUG_EVENT, "MBOX vector: 0x%x", vector); in wl18xx_process_mailbox_events() 126 mbox->number_of_scan_results); in wl18xx_process_mailbox_events() 128 if (wl->scan_wlvif) in wl18xx_process_mailbox_events() [all …]
|
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/ |
H A D | octep_vf_cn9k.c | 1 // SPDX-License-Identifier: GPL-2.0 19 struct device *dev = &oct->pdev->dev; in cn93_vf_dump_q_regs() 21 dev_info(dev, "IQ-%d register dump\n", qno); in cn93_vf_dump_q_regs() 50 dev_info(dev, "OQ-%d register dump\n", qno); in cn93_vf_dump_q_regs() 85 dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no); in cn93_vf_reset_iq() 105 /* Reset Hardware Rx queue */ 110 /* Disable Output (Rx) Ring */ in cn93_vf_reset_oq() 121 /* Reset all hardware Tx/Rx queues */ 124 struct pci_dev *pdev = oct->pdev; in octep_vf_reset_io_queues_cn93() 127 dev_dbg(&pdev->dev, "Reset OCTEP_CN93 VF IO Queues\n"); in octep_vf_reset_io_queues_cn93() [all …]
|