Lines Matching +full:mbox +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0
29 /* TX0/RX0/RXDB[0-3] */
42 /* Please not change TX & RX */
45 IMX_MU_TYPE_RX = 1, /* Rx */
47 IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */
93 struct mbox_controller mbox;
117 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
127 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
128 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
129 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
132 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
134 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
136 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
138 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
144 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
146 return container_of(mbox, struct imx_mu_priv, mbox);
151 iowrite32(val, priv->base + offs);
156 return ioread32(priv->base + offs);
165 dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx);
168 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
169 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
173 dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n",
175 return -ETIME;
178 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);
189 dev_dbg(priv->dev, "Trying to read from idx %d\n", idx);
192 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
193 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
197 dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n",
199 return -ETIME;
202 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);
203 dev_dbg(priv->dev, "Read %.8x\n", *val);
213 spin_lock_irqsave(&priv->xcr_lock, flags);
214 val = imx_mu_read(priv, priv->dcfg->xCR[type]);
217 imx_mu_write(priv, val, priv->dcfg->xCR[type]);
218 spin_unlock_irqrestore(&priv->xcr_lock, flags);
231 switch (cp->type) {
233 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
234 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
237 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
238 queue_work(system_bh_wq, &cp->txdb_work);
241 imx_mu_write(priv, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx),
242 priv->dcfg->xCR[IMX_MU_GCR]);
243 ret = -ETIMEDOUT;
247 readl_poll_timeout(priv->base + priv->dcfg->xCR[IMX_MU_GCR], val,
248 !(val & IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx)),
252 dev_warn_ratelimited(priv->dev,
254 cp->type, ++count);
259 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
260 return -EINVAL;
271 dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
272 mbox_chan_received_data(cp->chan, (void *)&dat);
280 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
281 priv->dcfg->xSR[IMX_MU_GSR]);
282 mbox_chan_received_data(cp->chan, NULL);
290 u32 num_tr = priv->num_tr;
295 if (priv->dcfg->type & IMX_MU_V2_S4) {
296 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
299 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
303 switch (cp->type) {
306 * msg->hdr.size specifies the number of u32 words while
315 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2);
316 return -EINVAL;
320 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
322 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
324 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
327 dev_err(priv->dev, "Send data index: %d timeout\n", i);
330 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
333 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
336 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
337 return -EINVAL;
349 u32 num_rr = priv->num_rr;
351 data = (u32 *)priv->msg;
353 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
354 *data++ = imx_mu_read(priv, priv->dcfg->xRR);
356 if (priv->dcfg->type & IMX_MU_V2_S4) {
357 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size;
360 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size;
365 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2);
366 return -EINVAL;
370 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
371 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0,
374 dev_err(priv->dev, "timeout read idx %d\n", i);
377 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4);
380 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
381 mbox_chan_received_data(cp->chan, (void *)priv->msg);
395 dev_dbg(priv->dev, "Sending message\n");
397 switch (cp->type) {
399 byte_size = msg->hdr.size * sizeof(u32);
405 dev_err(priv->dev,
408 return -EINVAL;
415 dev_dbg(priv->dev, "Sending header\n");
416 imx_mu_write(priv, *arg++, priv->dcfg->xTR);
419 dev_dbg(priv->dev, "Sending signaling\n");
421 IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
424 for (i = 1; i < 4 && i < msg->hdr.size; i++) {
425 dev_dbg(priv->dev, "Sending word %d\n", i);
427 priv->dcfg->xTR + (i % 4) * 4);
431 for (; i < msg->hdr.size; i++) {
432 dev_dbg(priv->dev, "Sending word %d\n", i);
435 dev_err(priv->dev, "Timeout tx %d\n", i);
440 /* Simulate hack for mbox framework */
441 queue_work(system_bh_wq, &cp->txdb_work);
445 dev_warn_ratelimited(priv->dev,
447 cp->type);
448 return -EINVAL;
462 dev_dbg(priv->dev, "Receiving message\n");
465 dev_dbg(priv->dev, "Receiving header\n");
466 *data++ = imx_mu_read(priv, priv->dcfg->xRR);
469 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",
471 err = -EINVAL;
477 dev_dbg(priv->dev, "Receiving word %d\n", i);
480 dev_err(priv->dev, "Timeout rx %d\n", i);
486 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
487 priv->dcfg->xSR[IMX_MU_GSR]);
493 dev_dbg(priv->dev, "Sending message to client\n");
494 mbox_chan_received_data(cp->chan, (void *)&msg);
499 mbox_chan_received_data(cp->chan, ERR_PTR(err));
509 mbox_chan_txdone(cp->chan, 0);
515 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
516 struct imx_mu_con_priv *cp = chan->con_priv;
519 switch (cp->type) {
521 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
522 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
523 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
524 (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
527 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
528 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
529 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
530 (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
533 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);
534 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
535 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
536 (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
541 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",
542 cp->type);
549 if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
550 (cp->type == IMX_MU_TYPE_TX)) {
551 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
553 } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
554 (cp->type == IMX_MU_TYPE_RX)) {
555 priv->dcfg->rx(priv, cp);
556 } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
557 (cp->type == IMX_MU_TYPE_RXDB)) {
558 priv->dcfg->rxdb(priv, cp);
560 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
564 if (priv->suspend)
572 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
573 struct imx_mu_con_priv *cp = chan->con_priv;
575 return priv->dcfg->tx(priv, cp, data);
580 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
581 struct imx_mu_con_priv *cp = chan->con_priv;
585 pm_runtime_get_sync(priv->dev);
586 if (cp->type == IMX_MU_TYPE_TXDB_V2)
589 if (cp->type == IMX_MU_TYPE_TXDB) {
591 INIT_WORK(&cp->txdb_work, imx_mu_txdb_work);
596 if (!priv->dev->pm_domain)
599 if (!(priv->dcfg->type & IMX_MU_V2_IRQ))
602 ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan);
604 dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]);
608 switch (cp->type) {
610 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
613 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
624 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
625 struct imx_mu_con_priv *cp = chan->con_priv;
629 if (cp->type == IMX_MU_TYPE_TXDB_V2) {
630 pm_runtime_put_sync(priv->dev);
634 if (cp->type == IMX_MU_TYPE_TXDB) {
635 cancel_work_sync(&cp->txdb_work);
636 pm_runtime_put_sync(priv->dev);
640 switch (cp->type) {
642 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
645 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
648 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
651 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);
652 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr,
653 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);
655 dev_warn(priv->dev, "RST channel timeout\n");
661 free_irq(priv->irq[cp->type], chan);
662 pm_runtime_put_sync(priv->dev);
671 static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox,
676 if (sp->args_count != 2) {
677 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
678 return ERR_PTR(-EINVAL);
681 type = sp->args[0]; /* channel type */
682 idx = sp->args[1]; /* index */
688 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
695 dev_err(mbox->dev, "Invalid chan type: %d\n", type);
696 return ERR_PTR(-EINVAL);
699 if (chan >= mbox->num_chans) {
700 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
701 return ERR_PTR(-EINVAL);
704 return &mbox->chans[chan];
707 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
713 if (sp->args_count != 2) {
714 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
715 return ERR_PTR(-EINVAL);
718 type = sp->args[0]; /* channel type */
719 idx = sp->args[1]; /* index */
723 dev_err(mbox->dev, "Invalid RST channel %d\n", idx);
724 return ERR_PTR(-EINVAL);
728 if (chan >= mbox->num_chans) {
729 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
730 return ERR_PTR(-EINVAL);
733 p_chan = &mbox->chans[chan];
736 p_chan->txdone_method = TXDONE_BY_ACK;
741 static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
746 if (sp->args_count < 1) {
747 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
748 return ERR_PTR(-EINVAL);
751 type = sp->args[0]; /* channel type */
755 dev_err(mbox->dev, "Invalid type: %d\n", type);
756 return ERR_PTR(-EINVAL);
759 return imx_mu_xlate(mbox, sp);
766 if (priv->dcfg->type & IMX_MU_V2) {
768 priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
769 priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val);
771 priv->num_tr = 4;
772 priv->num_rr = 4;
781 if (priv->num_rr > 4 || priv->num_tr > 4) {
783 return -EOPNOTSUPP;
787 struct imx_mu_con_priv *cp = &priv->con_priv[i];
789 cp->idx = i % 4;
790 cp->type = i >> 2;
791 cp->chan = &priv->mbox_chans[i];
792 priv->mbox_chans[i].con_priv = cp;
793 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
794 "%s[%i-%u]", dev_name(priv->dev), cp->type, cp->idx);
797 priv->mbox.num_chans = IMX_MU_CHANS;
798 priv->mbox.of_xlate = imx_mu_xlate;
800 if (priv->side_b)
805 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
808 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
809 imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
812 for (i = 0; i < priv->num_rr; i++)
813 imx_mu_read(priv, priv->dcfg->xRR + i * 4);
821 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
824 struct imx_mu_con_priv *cp = &priv->con_priv[i];
826 cp->idx = i < 2 ? 0 : i - 2;
827 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
828 cp->chan = &priv->mbox_chans[i];
829 priv->mbox_chans[i].con_priv = cp;
830 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
831 "%s[%i-%u]", dev_name(priv->dev), cp->type, cp->idx);
834 priv->mbox.num_chans = num_chans;
835 priv->mbox.of_xlate = imx_mu_specific_xlate;
839 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
851 priv->mbox.of_xlate = imx_mu_seco_xlate;
858 struct device *dev = &pdev->dev;
859 struct device_node *np = dev->of_node;
867 return -ENOMEM;
869 priv->dev = dev;
871 priv->base = devm_platform_ioremap_resource(pdev, 0);
872 if (IS_ERR(priv->base))
873 return PTR_ERR(priv->base);
877 return -EINVAL;
878 priv->dcfg = dcfg;
879 if (priv->dcfg->type & IMX_MU_V2_IRQ) {
880 priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx");
881 if (priv->irq[IMX_MU_TYPE_TX] < 0)
882 return priv->irq[IMX_MU_TYPE_TX];
883 priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx");
884 if (priv->irq[IMX_MU_TYPE_RX] < 0)
885 return priv->irq[IMX_MU_TYPE_RX];
892 priv->irq[i] = ret;
895 if (priv->dcfg->type & IMX_MU_V2_S4)
900 priv->msg = devm_kzalloc(dev, size, GFP_KERNEL);
901 if (!priv->msg)
902 return -ENOMEM;
904 priv->clk = devm_clk_get(dev, NULL);
905 if (IS_ERR(priv->clk)) {
906 if (PTR_ERR(priv->clk) != -ENOENT)
907 return PTR_ERR(priv->clk);
909 priv->clk = NULL;
912 ret = clk_prepare_enable(priv->clk);
920 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
922 ret = priv->dcfg->init(priv);
928 spin_lock_init(&priv->xcr_lock);
930 priv->mbox.dev = dev;
931 priv->mbox.ops = &imx_mu_ops;
932 priv->mbox.chans = priv->mbox_chans;
933 priv->mbox.txdone_irq = true;
937 ret = devm_mbox_controller_register(dev, &priv->mbox);
941 of_platform_populate(dev->of_node, NULL, NULL, dev);
953 clk_disable_unprepare(priv->clk);
960 clk_disable_unprepare(priv->clk);
968 pm_runtime_disable(priv->dev);
973 .rx = imx_mu_generic_rx,
984 .rx = imx_mu_generic_rx,
995 .rx = imx_mu_generic_rx,
1007 .rx = imx_mu_specific_rx,
1018 .rx = imx_mu_specific_rx,
1029 .rx = imx_mu_specific_rx,
1040 .rx = imx_mu_generic_rx,
1050 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
1051 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
1052 { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
1053 { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
1054 { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
1055 { .compatible = "fsl,imx95-mu", .data = &imx_mu_cfg_imx8ulp },
1056 { .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 },
1057 { .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 },
1058 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
1059 { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
1069 if (!priv->clk) {
1071 priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
1074 priv->suspend = true;
1092 if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) {
1094 imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
1097 priv->suspend = false;
1106 clk_disable_unprepare(priv->clk);
1116 ret = clk_prepare_enable(priv->clk);