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/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A Dtlb.json12 …e broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 …s from both data and instruction fetch, except for those caused by TLB maintenance operations and …
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
32 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
44 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
48 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
52 …ns from both data and instruction fetch except for those caused by TLB maintenance operations or h…
56 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
60 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
[all …]
H A Dl1d_cache.json12 …victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The…
44 …cache line allocation. This event does not count evictions caused by cache maintenance operations."
48 …t of a coherency operation made by another CPU. Event count includes cache maintenance operations."
52 …dation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO…
H A Dl2_cache.json40 …-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n…
44 …maintenance operations that operate by a virtual address, or by external coherency operations. Thi…
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A Dtlb.json12 "PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operation. Note that load or store instructions can be broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 "PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch, except for those caused by TLB maintenance operations and hardware prefetches."
24 "PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operations."
28 "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
32 "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations."
44 "PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This event counts whether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
48 "PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This event counts whether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
52 "PublicDescription": "Counts level 2 TLB refills caused by memory read operations from both data and instruction fetch except for those caused by TLB maintenance operations or hardware prefetches."
56 "PublicDescription": "Counts level 2 TLB refills caused by memory write operations from both data and instruction fetch except for those caused by TLB maintenance operations."
60 "PublicDescription": "Counts level 2 TLB accesses caused by memory read operations from both data and instruction fetch except for those caused by TLB maintenance operation
[all...]
H A Dl1d_cache.json12 "PublicDescription": "Counts write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache line is evicted from L1 data cache and allocated in the L2 cache or dirty data is written to the L2 and possibly to the next level of cache. This event counts both victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidations which do not result in data being transferred out of the L1 (such as evictions of clean data),\n2. Full line writes which write to L2 without writing L1, such as write streaming mode."
44 "PublicDescription": "Counts dirty cache line evictions from the level 1 data cache caused by a new cache line allocation. This event does not count evictions caused by cache maintenance operations."
48 "PublicDescription": "Counts write-backs from the level 1 data cache that are a result of a coherency operation made by another CPU. Event count includes cache maintenance operations."
52 "PublicDescription": "Counts each explicit invalidation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coherency operations from another CPU in the system.\n\nThis event does not count for the following conditions:\n\n1. A cache refill invalidates a cache line.\n2. A CMO which is executed on that CPU and invalidates a cache line specified by set/way.\n\nNote that CMOs that operate by set/way cannot be broadcast from one CPU to another."
H A Dl2_cache.json40 "PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n2. Snoop responses or,\n\n3. Direct cache transfers to another CPU due to a forwarding snoop request."
44 "PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by cache maintenance operations that operate by a virtual address, or by external coherency operations. This event does not count if either:\n\n1. A cache refill invalidates a cache line or,\n2. A Cache Maintenance Operation (CMO), which invalidates a cache line specified by set/way, is executed on that CPU.\n\nCMOs that operate by set/way cannot be broadcast from one CPU to another."
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dtlb.json12 …e broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 …s from both data and instruction fetch, except for those caused by TLB maintenance operations and …
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
32 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
44 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
48 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
52 …ns from both data and instruction fetch except for those caused by TLB maintenance operations or h…
56 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
60 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
[all …]
H A Dl1d_cache.json12 …victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The…
40 …cache line allocation. This event does not count evictions caused by cache maintenance operations."
44 …t of a coherency operation made by another CPU. Event count includes cache maintenance operations."
48 …dation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO…
H A Dl2_cache.json40 …-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n…
44 …maintenance operations that operate by a virtual address, or by external coherency operations. Thi…
H A Dl1i_cache.json8 … level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are …
/linux/arch/powerpc/sysdev/
H A Dfsl_rio.c7 * - fixed maintenance access routines, check for aligned access
136 * @len: Length (in bytes) of the maintenance transaction
158 * @len: Length (in bytes) of the maintenance transaction
177 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
183 * @len: Length (in bytes) of the maintenance transaction
186 * Generates a MPC85xx read maintenance transaction. Returns %0 on
203 /* 16MB maintenance window possible */ in fsl_rio_config_read()
204 /* allow only aligned access to maintenance registers */ in fsl_rio_config_read()
242 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
248 * @len: Length (in bytes) of the maintenance transaction
[all …]
H A Dfsl_rio.h7 * - fixed maintenance access routines, check for aligned access
39 #define DOORBELL_ROWAR_MAINTRD 0x00070000 /* maintenance read */
/linux/Documentation/driver-api/rapidio/
H A Dtsi721.rst9 It supports maintenance read and write operations, inbound and outbound RapidIO
10 doorbells, inbound maintenance port-writes and RapidIO messaging.
12 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
78 One BDMA channel is reserved for generation of maintenance read/write requests.
/linux/Documentation/arch/riscv/
H A Dpatch-acceptance.rst3 arch/riscv maintenance guidelines for developers
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
50 Foundation. To avoid the maintenance complexity and potential
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dsrio.txt64 memory and maintenance transactions then a single LIODN is
68 memory transactions and a unique LIODN for maintenance
72 represents the LIODN associated with maintenance transactions
/linux/include/uapi/misc/
H A Dfastrpc.h24 * The driver is responsible for cache maintenance when passed
30 * CPU and DSP cache maintenance for the buffer. Get virtual address
35 * cache maintenance for the buffer.
/linux/arch/arm/include/asm/
H A Dswitch_to.h10 * during a TLB maintenance operation, so execute an inner-shareable dsb
11 * to ensure that the maintenance completes in case we migrate to another
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/
H A Dmmu.json39 …: "Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA t…
42 …: "Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA t…
/linux/include/linux/
H A Dmemregion.h32 * Perform cache maintenance after a memory event / operation that
46 * the cache maintenance.
/linux/Documentation/maintainer/
H A Dfeature-and-driver-maintainers.rst22 The amount of maintenance work is usually proportional to the size
128 foundation of kernel maintenance and one cannot build trust with a mailing
163 Subsystem maintainers may remove code for lacking maintenance.
/linux/drivers/soc/bcm/brcmstb/
H A Dbiuctrl.c159 * The read-ahead cache is transparent for Virtual Address cache maintenance
166 * for the IC IALLU and IC IALLUIS cache maintenance operations.
169 * maintenance instructions operating by set/way to operate on the read-ahead
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/
H A Dcache.json27 …or L3. This counts both victim line evictions and snoops, including cache maintenance operations.",
31 …ite-back from the L1 to the L2. Snoops from outside the core and cache maintenance operations are …
/linux/arch/arm64/include/asm/
H A Dcacheflush.h92 * KGDB performs cache maintenance with interrupts disabled, so we in flush_icache_range()
95 * just means that KGDB will elide the maintenance altogether! As it in flush_icache_range()
/linux/arch/arm/mm/
H A Dcache-b15-rac.c48 * into the v7 cache maintenance operations during suspend/resume
137 * cache maintenance operations: ICIMVAU, DCIMVAC, DCCMVAC, DCCMVAU and
140 * It is however not transparent for the following cache maintenance
/linux/arch/powerpc/platforms/powernv/
H A Dopal-hmi.c3 * OPAL hypervisor Maintenance interrupt handling support in PowerNV.
54 "Recovery in maintenance mode" }, in print_core_checkstop_reason()
246 printk("%s%s Hypervisor Maintenance interrupt [%s]\n", in print_hmi_event_info()

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