| /linux/Documentation/edac/ |
| H A D | memory_repair.rst | 27 Post Package Repair is a maintenance operation which requests the memory
33 features implements maintenance operations. DRAM components support those
47 8.2.9.7.1.1 PPR Maintenance Operations, 8.2.9.7.1.2 sPPR Maintenance Operation
48 and 8.2.9.7.1.3 hPPR Maintenance Operation for more details.
77 See CXL spec 3.1 [1]_ section 8.2.9.7.1.4 Memory Sparing Maintenance
91 host of the need for a repair maintenance operation by using an event
92 record where the "maintenance needed" flag is set. The event record
96 rasdaemon) initiate a repair maintenance operation in response to the
100 region when maintenance need flag set or an uncorrected memory error or
135 Memory sparing maintenance operations may be supported by CXL devices that
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | tlb.json | 12 …e broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 …s from both data and instruction fetch, except for those caused by TLB maintenance operations and …
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
32 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
44 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
48 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
52 …ns from both data and instruction fetch except for those caused by TLB maintenance operations or h…
56 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
60 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
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| H A D | l1d_cache.json | 12 …victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The…
44 …cache line allocation. This event does not count evictions caused by cache maintenance operations."
48 …t of a coherency operation made by another CPU. Event count includes cache maintenance operations."
52 …dation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO…
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| H A D | l2_cache.json | 40 …-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n…
44 …maintenance operations that operate by a virtual address, or by external coherency operations. Thi…
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| H A D | l1i_cache.json | 8 … level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are …
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | tlb.json | 12 …e broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 …s from both data and instruction fetch, except for those caused by TLB maintenance operations and …
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
32 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
44 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
48 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
52 …ns from both data and instruction fetch except for those caused by TLB maintenance operations or h…
56 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
60 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
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| H A D | l1d_cache.json | 12 …victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The…
40 …cache line allocation. This event does not count evictions caused by cache maintenance operations."
44 …t of a coherency operation made by another CPU. Event count includes cache maintenance operations."
48 …dation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO…
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| H A D | l2_cache.json | 40 …-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n…
44 …maintenance operations that operate by a virtual address, or by external coherency operations. Thi…
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| H A D | l1i_cache.json | 8 … level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are …
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| /linux/arch/powerpc/sysdev/ |
| H A D | fsl_rio.c | 7 * - fixed maintenance access routines, check for aligned access
136 * @len: Length (in bytes) of the maintenance transaction
158 * @len: Length (in bytes) of the maintenance transaction
177 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
183 * @len: Length (in bytes) of the maintenance transaction
186 * Generates a MPC85xx read maintenance transaction. Returns %0 on
203 /* 16MB maintenance window possible */ in fsl_rio_config_read()
204 /* allow only aligned access to maintenance registers */ in fsl_rio_config_read()
242 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
248 * @len: Length (in bytes) of the maintenance transaction
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| H A D | fsl_rio.h | 7 * - fixed maintenance access routines, check for aligned access
39 #define DOORBELL_ROWAR_MAINTRD 0x00070000 /* maintenance read */
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| /linux/Documentation/driver-api/rapidio/ |
| H A D | tsi721.rst | 9 It supports maintenance read and write operations, inbound and outbound RapidIO
10 doorbells, inbound maintenance port-writes and RapidIO messaging.
12 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
78 One BDMA channel is reserved for generation of maintenance read/write requests.
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| /linux/Documentation/arch/riscv/ |
| H A D | patch-acceptance.rst | 3 arch/riscv maintenance guidelines for developers
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
50 Foundation. To avoid the maintenance complexity and potential
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | srio.txt | 64 memory and maintenance transactions then a single LIODN is
68 memory transactions and a unique LIODN for maintenance
72 represents the LIODN associated with maintenance transactions
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| /linux/include/uapi/misc/ |
| H A D | fastrpc.h | 24 * The driver is responsible for cache maintenance when passed
30 * CPU and DSP cache maintenance for the buffer. Get virtual address
35 * cache maintenance for the buffer.
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| /linux/arch/arm/include/asm/ |
| H A D | switch_to.h | 10 * during a TLB maintenance operation, so execute an inner-shareable dsb
11 * to ensure that the maintenance completes in case we migrate to another
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/ |
| H A D | mmu.json | 39 …: "Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA t…
42 …: "Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA t…
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| /linux/include/linux/ |
| H A D | memregion.h | 32 * Perform cache maintenance after a memory event / operation that
46 * the cache maintenance.
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| /linux/Documentation/maintainer/ |
| H A D | feature-and-driver-maintainers.rst | 22 The amount of maintenance work is usually proportional to the size
128 foundation of kernel maintenance and one cannot build trust with a mailing
163 Subsystem maintainers may remove code for lacking maintenance.
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| /linux/arch/arm/ |
| H A D | Kconfig | 642 corrects this value, ensuring cache maintenance operations which use
651 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
723 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
729 cache line maintenance operation by MVA targeting an Inner
733 relevant cache maintenance functions and sets a specific bit
748 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
752 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
755 an abort may occur on cache maintenance.
868 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
871 The v7 ARM states that all cache and branch predictor maintenance
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| /linux/drivers/soc/bcm/brcmstb/ |
| H A D | biuctrl.c | 159 * The read-ahead cache is transparent for Virtual Address cache maintenance
166 * for the IC IALLU and IC IALLUIS cache maintenance operations.
169 * maintenance instructions operating by set/way to operate on the read-ahead
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| H A D | cache.json | 27 …or L3. This counts both victim line evictions and snoops, including cache maintenance operations.",
31 …ite-back from the L1 to the L2. Snoops from outside the core and cache maintenance operations are …
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| /linux/arch/arm64/include/asm/ |
| H A D | cacheflush.h | 92 * KGDB performs cache maintenance with interrupts disabled, so we in flush_icache_range()
95 * just means that KGDB will elide the maintenance altogether! As it in flush_icache_range()
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| /linux/arch/arm/mm/ |
| H A D | cache-b15-rac.c | 48 * into the v7 cache maintenance operations during suspend/resume
137 * cache maintenance operations: ICIMVAU, DCIMVAC, DCCMVAC, DCCMVAU and
140 * It is however not transparent for the following cache maintenance
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| /linux/arch/powerpc/platforms/powernv/ |
| H A D | opal-hmi.c | 3 * OPAL hypervisor Maintenance interrupt handling support in PowerNV.
54 "Recovery in maintenance mode" }, in print_core_checkstop_reason()
246 printk("%s%s Hypervisor Maintenance interrupt [%s]\n", in print_hmi_event_info()
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