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/linux/arch/arm/boot/dts/st/
H A Dstm32mp135.dtsi23 ltdc: display-controller@5a001000 { label
24 compatible = "st,stm32-ltdc";
H A Dstm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts78 &ltdc {
91 ltdc_pins: ltdc-0 {
H A Dstm32f429-disco.dts156 &ltdc {
194 /* Connect panel-ilitek-9341 to ltdc */
H A Dstm32mp157a-icore-stm32mp1-ctouch2-of10.dts94 &ltdc {
H A Dstm32mp157a-icore-stm32mp1-edimm2.2.dts94 &ltdc {
H A Dstm32f746.dtsi635 ltdc: display-controller@40016800 { label
636 compatible = "st,stm32-ltdc";
639 resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
H A Dstm32f429.dtsi671 ltdc: display-controller@40016800 { label
672 compatible = "st,stm32-ltdc";
675 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
H A Dstm32h743.dtsi361 ltdc: display-controller@50001000 { label
362 compatible = "st,stm32-ltdc";
365 resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
H A Dstm32mp157c-osd32mp1-red.dts133 &ltdc {
H A Dstm32f469-disco.dts171 &ltdc {
H A Dstm32f769-disco.dts180 &ltdc {
H A Dstm32f746-disco.dts169 &ltdc {
H A Dstm32f4-pinctrl.dtsi284 ltdc_pins_a: ltdc-0 {
318 ltdc_pins_b: ltdc-1 {
H A Dstm32mp157c-lxa-mc1.dts157 &ltdc {
H A Dstm32429i-eval.dts240 &ltdc {
H A Dstm32mp15xx-dhcor-avenger96.dtsi354 &ltdc {
H A Dstm32f7-pinctrl.dtsi401 ltdc_pins_a: ltdc-0 {
H A Dstm32mp135f-dk.dts348 &ltdc {
H A Dstm32mp13-pinctrl.dtsi328 ltdc_pins_a: ltdc-0 {
359 ltdc_sleep_pins_a: ltdc-sleep-0 {
/linux/drivers/gpu/drm/stm/
H A DMakefile4 ltdc.o
H A Ddw_mipi_dsi-stm.c573 * resync with LTDC pixel clock. in dw_mipi_dsi_stm_mode_valid()
/linux/Documentation/devicetree/bindings/display/
H A Dst,stm32-dsi.yaml58 DSI input port node, connected to the ltdc rgb output port.
/linux/include/dt-bindings/clock/
H A Dstm32mp1-clks.h69 #define LTDC 56 macro
/linux/drivers/clk/stm32/
H A Dclk-stm32mp1.c1940 PCLK(LTDC, "ltdc", "pclk4", 0, G_LTDC),
/linux/drivers/clk/
H A Dclk-stm32h7.c1107 KER_CLKF_NOMUX(RCC_APB3ENR, 3, "ltdc", ltdc_src, CLK_SET_RATE_PARENT),

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