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Searched +full:ls1088a +full:- +full:pcie (Results 1 – 8 of 8) sorted by relevance

/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "fsl,ls1088a";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
4 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
5 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
6 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
7 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
8 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb
9 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb
10 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var1.dtb
11 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb
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H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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/linux/Documentation/devicetree/bindings/pci/
H A Dfsl,layerscape-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape PCIe Root Complex(RC) controller
10 - Frank Li <Frank.Li@nxp.com>
13 This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
16 which is used to describe the PLL settings at the time of chip-reset.
19 register available in the Freescale PCIe controller register set,
20 which can allow determining the underlying DesignWare PCIe controller version
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/linux/Documentation/devicetree/bindings/mfd/
H A Dsyscon.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
20 - Lee Jones <lee@kernel.org>
30 - al,alpine-sysfabric-servic
31 - allwinner,sun8i-a83t-system-controller
32 - allwinner,sun8i-h3-system-controller
33 - allwinner,sun8i-v3s-system-controller
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/linux/drivers/pci/controller/dwc/
H A Dpci-layerscape-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe controller EP driver for Freescale Layerscape SoCs
19 #include "pcie-designware.h"
24 /* PEX PFa PCIE PME and message interrupt registers*/
35 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
52 static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset) in ls_pcie_pf_lut_readl() argument
54 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_readl()
56 if (pcie->big_endian) in ls_pcie_pf_lut_readl()
57 return ioread32be(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()
59 return ioread32(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()
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H A Dpci-layerscape.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Freescale Layerscape SoCs
26 #include "pcie-designware.h"
31 #define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
46 #define PEXPME(idx) BIT(31 - (idx) * 4)
72 #define ls_pcie_pf_lut_readl_addr(addr) ls_pcie_pf_lut_readl(pcie, addr)
73 #define to_ls_pcie(x) dev_get_drvdata((x)->dev)
75 static bool ls_pcie_is_bridge(struct ls_pcie *pcie) in ls_pcie_is_bridge() argument
77 struct dw_pcie *pci = pcie->pci; in ls_pcie_is_bridge()
80 header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE); in ls_pcie_is_bridge()
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