Searched +full:ls1088a +full:- +full:pcie (Results 1 – 5 of 5) sorted by relevance
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for NXP Layerscape-1088A family SoC.5 * Copyright 2017-2020 NXP10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include <dt-bindings/thermal/thermal.h>15 compatible = "fsl,ls1088a";16 interrupt-parent = <&gic>;17 #address-cells = <2>;18 #size-cells = <2>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.6 * Copyright 2017-2020 NXP12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>13 #include <dt-bindings/thermal/thermal.h>14 #include <dt-bindings/interrupt-controller/arm-gic.h>18 interrupt-parent = <&gic>;19 #address-cells = <2>;20 #size-cells = <2>;32 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)3 // Device Tree Include file for Layerscape-LX2160A family SoC.5 // Copyright 2018-2020 NXP7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/thermal/thermal.h>16 interrupt-parent = <&gic>;17 #address-cells = <2>;18 #size-cells = <2>;[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Freescale Layerscape PCIe Root Complex(RC) controller10 - Frank Li <Frank.Li@nxp.com>13 This PCIe RC controller is based on the Synopsys DesignWare PCIe IP16 which is used to describe the PLL settings at the time of chip-reset.19 register available in the Freescale PCIe controller register set,20 which can allow determining the underlying DesignWare PCIe controller version[all …]
1 // SPDX-License-Identifier: GPL-2.03 * PCIe controller EP driver for Freescale Layerscape SoCs19 #include "pcie-designware.h"24 /* PEX PFa PCIE PME and message interrupt registers*/35 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)52 static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset) in ls_pcie_pf_lut_readl() argument54 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_readl()56 if (pcie->big_endian) in ls_pcie_pf_lut_readl()57 return ioread32be(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()59 return ioread32(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()[all …]