Lines Matching +full:ls1088a +full:- +full:pcie
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 // 8 clusters having 2 Cortex-A72 cores each
31 compatible = "arm,cortex-a72";
32 enable-method = "psci";
35 d-cache-size = <0x8000>;
36 d-cache-line-size = <64>;
37 d-cache-sets = <128>;
38 i-cache-size = <0xC000>;
39 i-cache-line-size = <64>;
40 i-cache-sets = <192>;
41 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cpu_pw15>;
43 #cooling-cells = <2>;
48 compatible = "arm,cortex-a72";
49 enable-method = "psci";
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
54 d-cache-sets = <128>;
55 i-cache-size = <0xC000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <192>;
58 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cpu_pw15>;
60 #cooling-cells = <2>;
65 compatible = "arm,cortex-a72";
66 enable-method = "psci";
69 d-cache-size = <0x8000>;
70 d-cache-line-size = <64>;
71 d-cache-sets = <128>;
72 i-cache-size = <0xC000>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <192>;
75 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cpu_pw15>;
77 #cooling-cells = <2>;
82 compatible = "arm,cortex-a72";
83 enable-method = "psci";
86 d-cache-size = <0x8000>;
87 d-cache-line-size = <64>;
88 d-cache-sets = <128>;
89 i-cache-size = <0xC000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <192>;
92 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cpu_pw15>;
94 #cooling-cells = <2>;
99 compatible = "arm,cortex-a72";
100 enable-method = "psci";
103 d-cache-size = <0x8000>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 i-cache-size = <0xC000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <192>;
109 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cpu_pw15>;
111 #cooling-cells = <2>;
116 compatible = "arm,cortex-a72";
117 enable-method = "psci";
120 d-cache-size = <0x8000>;
121 d-cache-line-size = <64>;
122 d-cache-sets = <128>;
123 i-cache-size = <0xC000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <192>;
126 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cpu_pw15>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a72";
134 enable-method = "psci";
137 d-cache-size = <0x8000>;
138 d-cache-line-size = <64>;
139 d-cache-sets = <128>;
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <192>;
143 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cpu_pw15>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a72";
151 enable-method = "psci";
154 d-cache-size = <0x8000>;
155 d-cache-line-size = <64>;
156 d-cache-sets = <128>;
157 i-cache-size = <0xC000>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <192>;
160 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cpu_pw15>;
162 #cooling-cells = <2>;
167 compatible = "arm,cortex-a72";
168 enable-method = "psci";
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 i-cache-size = <0xC000>;
175 i-cache-line-size = <64>;
176 i-cache-sets = <192>;
177 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cpu_pw15>;
179 #cooling-cells = <2>;
184 compatible = "arm,cortex-a72";
185 enable-method = "psci";
188 d-cache-size = <0x8000>;
189 d-cache-line-size = <64>;
190 d-cache-sets = <128>;
191 i-cache-size = <0xC000>;
192 i-cache-line-size = <64>;
193 i-cache-sets = <192>;
194 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cpu_pw15>;
196 #cooling-cells = <2>;
201 compatible = "arm,cortex-a72";
202 enable-method = "psci";
205 d-cache-size = <0x8000>;
206 d-cache-line-size = <64>;
207 d-cache-sets = <128>;
208 i-cache-size = <0xC000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <192>;
211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cpu_pw15>;
213 #cooling-cells = <2>;
218 compatible = "arm,cortex-a72";
219 enable-method = "psci";
222 d-cache-size = <0x8000>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <128>;
225 i-cache-size = <0xC000>;
226 i-cache-line-size = <64>;
227 i-cache-sets = <192>;
228 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cpu_pw15>;
230 #cooling-cells = <2>;
235 compatible = "arm,cortex-a72";
236 enable-method = "psci";
239 d-cache-size = <0x8000>;
240 d-cache-line-size = <64>;
241 d-cache-sets = <128>;
242 i-cache-size = <0xC000>;
243 i-cache-line-size = <64>;
244 i-cache-sets = <192>;
245 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cpu_pw15>;
247 #cooling-cells = <2>;
252 compatible = "arm,cortex-a72";
253 enable-method = "psci";
256 d-cache-size = <0x8000>;
257 d-cache-line-size = <64>;
258 d-cache-sets = <128>;
259 i-cache-size = <0xC000>;
260 i-cache-line-size = <64>;
261 i-cache-sets = <192>;
262 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cpu_pw15>;
264 #cooling-cells = <2>;
269 compatible = "arm,cortex-a72";
270 enable-method = "psci";
273 d-cache-size = <0x8000>;
274 d-cache-line-size = <64>;
275 d-cache-sets = <128>;
276 i-cache-size = <0xC000>;
277 i-cache-line-size = <64>;
278 i-cache-sets = <192>;
279 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cpu_pw15>;
281 #cooling-cells = <2>;
286 compatible = "arm,cortex-a72";
287 enable-method = "psci";
290 d-cache-size = <0x8000>;
291 d-cache-line-size = <64>;
292 d-cache-sets = <128>;
293 i-cache-size = <0xC000>;
294 i-cache-line-size = <64>;
295 i-cache-sets = <192>;
296 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cpu_pw15>;
298 #cooling-cells = <2>;
301 cluster0_l2: l2-cache0 {
303 cache-unified;
304 cache-size = <0x100000>;
305 cache-line-size = <64>;
306 cache-sets = <1024>;
307 cache-level = <2>;
310 cluster1_l2: l2-cache1 {
312 cache-unified;
313 cache-size = <0x100000>;
314 cache-line-size = <64>;
315 cache-sets = <1024>;
316 cache-level = <2>;
319 cluster2_l2: l2-cache2 {
321 cache-unified;
322 cache-size = <0x100000>;
323 cache-line-size = <64>;
324 cache-sets = <1024>;
325 cache-level = <2>;
328 cluster3_l2: l2-cache3 {
330 cache-unified;
331 cache-size = <0x100000>;
332 cache-line-size = <64>;
333 cache-sets = <1024>;
334 cache-level = <2>;
337 cluster4_l2: l2-cache4 {
339 cache-unified;
340 cache-size = <0x100000>;
341 cache-line-size = <64>;
342 cache-sets = <1024>;
343 cache-level = <2>;
346 cluster5_l2: l2-cache5 {
348 cache-unified;
349 cache-size = <0x100000>;
350 cache-line-size = <64>;
351 cache-sets = <1024>;
352 cache-level = <2>;
355 cluster6_l2: l2-cache6 {
357 cache-unified;
358 cache-size = <0x100000>;
359 cache-line-size = <64>;
360 cache-sets = <1024>;
361 cache-level = <2>;
364 cluster7_l2: l2-cache7 {
366 cache-unified;
367 cache-size = <0x100000>;
368 cache-line-size = <64>;
369 cache-sets = <1024>;
370 cache-level = <2>;
373 cpu_pw15: cpu-pw15 {
374 compatible = "arm,idle-state";
375 idle-state-name = "PW15";
376 arm,psci-suspend-param = <0x0>;
377 entry-latency-us = <2000>;
378 exit-latency-us = <2000>;
379 min-residency-us = <6000>;
383 gic: interrupt-controller@6000000 {
384 compatible = "arm,gic-v3";
391 #interrupt-cells = <3>;
392 #address-cells = <2>;
393 #size-cells = <2>;
395 interrupt-controller;
398 its: msi-controller@6020000 {
399 compatible = "arm,gic-v3-its";
400 msi-controller;
401 #msi-cells = <1>;
407 compatible = "arm,armv8-timer";
415 compatible = "arm,cortex-a72-pmu";
420 compatible = "arm,psci-0.2";
425 // DRAM space - 1, size : 2 GB DRAM
430 ddr1: memory-controller@1080000 {
431 compatible = "fsl,qoriq-memory-controller";
434 little-endian;
437 ddr2: memory-controller@1090000 {
438 compatible = "fsl,qoriq-memory-controller";
441 little-endian;
444 // One clock unit-sysclk node which bootloader require during DT fix-up
446 compatible = "fixed-clock";
447 #clock-cells = <0>;
448 clock-frequency = <100000000>; // fixed up by bootloader
449 clock-output-names = "sysclk";
452 thermal-zones {
453 cluster6-7-thermal {
454 polling-delay-passive = <1000>;
455 polling-delay = <5000>;
456 thermal-sensors = <&tmu 0>;
459 cluster6_7_alert: cluster6-7-alert {
465 cluster6_7_crit: cluster6-7-crit {
472 cooling-maps {
475 cooling-device =
496 ddr-ctrl5-thermal {
497 polling-delay-passive = <1000>;
498 polling-delay = <5000>;
499 thermal-sensors = <&tmu 1>;
502 ddr-cluster5-alert {
508 ddr-cluster5-crit {
516 wriop-thermal {
517 polling-delay-passive = <1000>;
518 polling-delay = <5000>;
519 thermal-sensors = <&tmu 2>;
522 wriop-alert {
528 wriop-crit {
536 dce-thermal {
537 polling-delay-passive = <1000>;
538 polling-delay = <5000>;
539 thermal-sensors = <&tmu 3>;
542 dce-qbman-alert {
548 dce-qbman-crit {
556 ccn-thermal {
557 polling-delay-passive = <1000>;
558 polling-delay = <5000>;
559 thermal-sensors = <&tmu 4>;
562 ccn-dpaa-alert {
568 ccn-dpaa-crit {
576 cluster4-thermal {
577 polling-delay-passive = <1000>;
578 polling-delay = <5000>;
579 thermal-sensors = <&tmu 5>;
582 clust4-hsio3-alert {
588 clust4-hsio3-crit {
596 cluster2-3-thermal {
597 polling-delay-passive = <1000>;
598 polling-delay = <5000>;
599 thermal-sensors = <&tmu 6>;
602 cluster2-3-alert {
608 cluster2-3-crit {
618 compatible = "simple-bus";
619 #address-cells = <2>;
620 #size-cells = <2>;
622 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
625 compatible = "fsl,lynx-28g";
627 #phy-cells = <1>;
631 compatible = "fsl,lynx-28g";
633 #phy-cells = <1>;
638 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
639 fsl,sec-era = <10>;
640 #address-cells = <1>;
641 #size-cells = <1>;
645 dma-coherent;
649 compatible = "fsl,sec-v5.0-job-ring",
650 "fsl,sec-v4.0-job-ring";
656 compatible = "fsl,sec-v5.0-job-ring",
657 "fsl,sec-v4.0-job-ring";
663 compatible = "fsl,sec-v5.0-job-ring",
664 "fsl,sec-v4.0-job-ring";
670 compatible = "fsl,sec-v5.0-job-ring",
671 "fsl,sec-v4.0-job-ring";
677 clockgen: clock-controller@1300000 {
678 compatible = "fsl,lx2160a-clockgen";
680 #clock-cells = <2>;
685 compatible = "fsl,lx2160a-dcfg", "syscon";
687 little-endian;
691 compatible = "fsl,ls1028a-sfp";
695 clock-names = "sfp";
699 compatible = "fsl,lx2160a-isc", "syscon";
701 little-endian;
702 #address-cells = <1>;
703 #size-cells = <1>;
706 extirq: interrupt-controller@14 {
707 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
708 #interrupt-cells = <2>;
709 #address-cells = <0>;
710 interrupt-controller;
712 interrupt-map =
725 interrupt-map-mask = <0xf 0x0>;
730 compatible = "fsl,qoriq-tmu";
733 fsl,tmu-range = <0x800000e6 0x8001017d>;
734 fsl,tmu-calibration =
739 little-endian;
740 #thermal-sensor-cells = <1>;
744 compatible = "fsl,vf610-i2c";
745 #address-cells = <1>;
746 #size-cells = <0>;
749 clock-names = "ipg";
752 pinctrl-names = "default", "gpio";
753 pinctrl-0 = <&i2c0_scl>;
754 pinctrl-1 = <&i2c0_scl_gpio>;
755 scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
760 compatible = "fsl,vf610-i2c";
761 #address-cells = <1>;
762 #size-cells = <0>;
765 clock-names = "ipg";
768 pinctrl-names = "default", "gpio";
769 pinctrl-0 = <&i2c1_scl>;
770 pinctrl-1 = <&i2c1_scl_gpio>;
771 scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
776 compatible = "fsl,vf610-i2c";
777 #address-cells = <1>;
778 #size-cells = <0>;
781 clock-names = "ipg";
784 pinctrl-names = "default", "gpio";
785 pinctrl-0 = <&i2c2_scl>;
786 pinctrl-1 = <&i2c2_scl_gpio>;
787 scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
792 compatible = "fsl,vf610-i2c";
793 #address-cells = <1>;
794 #size-cells = <0>;
797 clock-names = "ipg";
800 pinctrl-names = "default", "gpio";
801 pinctrl-0 = <&i2c3_scl>;
802 pinctrl-1 = <&i2c3_scl_gpio>;
803 scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
808 compatible = "fsl,vf610-i2c";
809 #address-cells = <1>;
810 #size-cells = <0>;
813 clock-names = "ipg";
816 pinctrl-names = "default", "gpio";
817 pinctrl-0 = <&i2c4_scl>;
818 pinctrl-1 = <&i2c4_scl_gpio>;
819 scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
824 compatible = "fsl,vf610-i2c";
825 #address-cells = <1>;
826 #size-cells = <0>;
829 clock-names = "ipg";
832 pinctrl-names = "default", "gpio";
833 pinctrl-0 = <&i2c5_scl>;
834 pinctrl-1 = <&i2c5_scl_gpio>;
835 scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
840 compatible = "fsl,vf610-i2c";
841 #address-cells = <1>;
842 #size-cells = <0>;
845 clock-names = "ipg";
848 pinctrl-names = "default", "gpio";
849 pinctrl-0 = <&i2c6_scl>;
850 pinctrl-1 = <&i2c6_scl_gpio>;
851 scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
856 compatible = "fsl,vf610-i2c";
857 #address-cells = <1>;
858 #size-cells = <0>;
861 clock-names = "ipg";
864 pinctrl-names = "default", "gpio";
865 pinctrl-0 = <&i2c7_scl>;
866 pinctrl-1 = <&i2c7_scl_gpio>;
867 scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
872 compatible = "nxp,lx2160a-fspi";
873 #address-cells = <1>;
874 #size-cells = <0>;
877 reg-names = "fspi_base", "fspi_mmap";
883 clock-names = "fspi_en", "fspi";
888 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
889 #address-cells = <1>;
890 #size-cells = <0>;
895 clock-names = "dspi";
896 spi-num-chipselects = <5>;
897 bus-num = <0>;
902 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
903 #address-cells = <1>;
904 #size-cells = <0>;
909 clock-names = "dspi";
910 spi-num-chipselects = <5>;
911 bus-num = <1>;
916 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
917 #address-cells = <1>;
918 #size-cells = <0>;
923 clock-names = "dspi";
924 spi-num-chipselects = <5>;
925 bus-num = <2>;
930 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
935 dma-coherent;
936 voltage-ranges = <1800 1800 3300 3300>;
937 sdhci,auto-cmd12;
938 little-endian;
939 bus-width = <4>;
944 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
949 dma-coherent;
950 voltage-ranges = <1800 1800 3300 3300>;
951 sdhci,auto-cmd12;
952 broken-cd;
953 little-endian;
954 bus-width = <4>;
959 compatible = "fsl,lx2160ar1-flexcan";
965 clock-names = "ipg", "per";
966 fsl,clk-source = /bits/ 8 <0>;
971 compatible = "fsl,lx2160ar1-flexcan";
977 clock-names = "ipg", "per";
978 fsl,clk-source = /bits/ 8 <0>;
988 clock-names = "uartclk", "apb_pclk";
1000 clock-names = "uartclk", "apb_pclk";
1012 clock-names = "uartclk", "apb_pclk";
1024 clock-names = "uartclk", "apb_pclk";
1031 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
1034 gpio-controller;
1035 little-endian;
1036 #gpio-cells = <2>;
1037 interrupt-controller;
1038 #interrupt-cells = <2>;
1042 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
1045 gpio-controller;
1046 little-endian;
1047 #gpio-cells = <2>;
1048 interrupt-controller;
1049 #interrupt-cells = <2>;
1053 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
1056 gpio-controller;
1057 little-endian;
1058 #gpio-cells = <2>;
1059 interrupt-controller;
1060 #interrupt-cells = <2>;
1064 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
1067 gpio-controller;
1068 little-endian;
1069 #gpio-cells = <2>;
1070 interrupt-controller;
1071 #interrupt-cells = <2>;
1075 compatible = "arm,sbsa-gwdt";
1079 timeout-sec = <30>;
1082 rcpm: wakeup-controller@1e34040 {
1083 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1085 #fsl,rcpm-wakeup-cells = <7>;
1086 little-endian;
1090 compatible = "fsl,lx2160a-ftm-alarm";
1092 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1101 snps,quirk-frame-length-adjustment = <0x20>;
1102 usb3-lpm-capable;
1104 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1113 snps,quirk-frame-length-adjustment = <0x20>;
1114 usb3-lpm-capable;
1116 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1121 compatible = "fsl,lx2160a-ahci";
1124 reg-names = "ahci", "sata-ecc";
1128 dma-coherent;
1133 compatible = "fsl,lx2160a-ahci";
1136 reg-names = "ahci", "sata-ecc";
1140 dma-coherent;
1145 compatible = "fsl,lx2160a-ahci";
1148 reg-names = "ahci", "sata-ecc";
1152 dma-coherent;
1157 compatible = "fsl,lx2160a-ahci";
1160 reg-names = "ahci", "sata-ecc";
1164 dma-coherent;
1168 pcie1: pcie@3400000 {
1169 compatible = "fsl,lx2160a-pcie";
1172 reg-names = "csr_axi_slave", "config_axi_slave";
1176 interrupt-names = "aer", "pme", "intr";
1177 #address-cells = <3>;
1178 #size-cells = <2>;
1180 dma-coherent;
1181 apio-wins = <8>;
1182 ppio-wins = <8>;
1183 bus-range = <0x0 0xff>;
1184 … ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1185 msi-parent = <&its 0>;
1186 #interrupt-cells = <1>;
1187 interrupt-map-mask = <0 0 0 7>;
1188 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1192 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1196 pcie2: pcie@3500000 {
1197 compatible = "fsl,lx2160a-pcie";
1200 reg-names = "csr_axi_slave", "config_axi_slave";
1204 interrupt-names = "aer", "pme", "intr";
1205 #address-cells = <3>;
1206 #size-cells = <2>;
1208 dma-coherent;
1209 apio-wins = <8>;
1210 ppio-wins = <8>;
1211 bus-range = <0x0 0xff>;
1212 … ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1213 msi-parent = <&its 0>;
1214 #interrupt-cells = <1>;
1215 interrupt-map-mask = <0 0 0 7>;
1216 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1220 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1224 pcie3: pcie@3600000 {
1225 compatible = "fsl,lx2160a-pcie";
1228 reg-names = "csr_axi_slave", "config_axi_slave";
1232 interrupt-names = "aer", "pme", "intr";
1233 #address-cells = <3>;
1234 #size-cells = <2>;
1236 dma-coherent;
1237 apio-wins = <256>;
1238 ppio-wins = <24>;
1239 bus-range = <0x0 0xff>;
1240 … ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1241 msi-parent = <&its 0>;
1242 #interrupt-cells = <1>;
1243 interrupt-map-mask = <0 0 0 7>;
1244 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1248 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1252 pcie4: pcie@3700000 {
1253 compatible = "fsl,lx2160a-pcie";
1256 reg-names = "csr_axi_slave", "config_axi_slave";
1260 interrupt-names = "aer", "pme", "intr";
1261 #address-cells = <3>;
1262 #size-cells = <2>;
1264 dma-coherent;
1265 apio-wins = <8>;
1266 ppio-wins = <8>;
1267 bus-range = <0x0 0xff>;
1268 … ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1269 msi-parent = <&its 0>;
1270 #interrupt-cells = <1>;
1271 interrupt-map-mask = <0 0 0 7>;
1272 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1276 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1280 pcie5: pcie@3800000 {
1281 compatible = "fsl,lx2160a-pcie";
1284 reg-names = "csr_axi_slave", "config_axi_slave";
1288 interrupt-names = "aer", "pme", "intr";
1289 #address-cells = <3>;
1290 #size-cells = <2>;
1292 dma-coherent;
1293 apio-wins = <256>;
1294 ppio-wins = <24>;
1295 bus-range = <0x0 0xff>;
1296 … ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1297 msi-parent = <&its 0>;
1298 #interrupt-cells = <1>;
1299 interrupt-map-mask = <0 0 0 7>;
1300 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1304 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1308 pcie6: pcie@3900000 {
1309 compatible = "fsl,lx2160a-pcie";
1312 reg-names = "csr_axi_slave", "config_axi_slave";
1316 interrupt-names = "aer", "pme", "intr";
1317 #address-cells = <3>;
1318 #size-cells = <2>;
1320 dma-coherent;
1321 apio-wins = <8>;
1322 ppio-wins = <8>;
1323 bus-range = <0x0 0xff>;
1324 … ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1325 msi-parent = <&its 0>;
1326 #interrupt-cells = <1>;
1327 interrupt-map-mask = <0 0 0 7>;
1328 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1332 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1337 compatible = "arm,mmu-500";
1339 #iommu-cells = <1>;
1340 #global-interrupts = <14>;
1345 // global non-secure fault
1347 // combined non-secure
1349 // performance counter interrupts 0-9
1425 dma-coherent;
1429 compatible = "fsl,dpaa2-console";
1433 ptp-timer@8b95000 {
1434 compatible = "fsl,dpaa2-ptp";
1438 little-endian;
1439 fsl,extts-fifo;
1442 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1444 compatible = "fsl,fman-memac-mdio";
1447 #address-cells = <1>;
1448 #size-cells = <0>;
1449 little-endian;
1450 clock-frequency = <2500000>;
1457 compatible = "fsl,fman-memac-mdio";
1460 little-endian;
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1463 clock-frequency = <2500000>;
1470 compatible = "fsl,fman-memac-mdio";
1472 little-endian;
1473 #address-cells = <1>;
1474 #size-cells = <0>;
1477 pcs1: ethernet-phy@0 {
1483 compatible = "fsl,fman-memac-mdio";
1485 little-endian;
1486 #address-cells = <1>;
1487 #size-cells = <0>;
1490 pcs2: ethernet-phy@0 {
1496 compatible = "fsl,fman-memac-mdio";
1498 little-endian;
1499 #address-cells = <1>;
1500 #size-cells = <0>;
1503 pcs3: ethernet-phy@0 {
1509 compatible = "fsl,fman-memac-mdio";
1511 little-endian;
1512 #address-cells = <1>;
1513 #size-cells = <0>;
1516 pcs4: ethernet-phy@0 {
1522 compatible = "fsl,fman-memac-mdio";
1524 little-endian;
1525 #address-cells = <1>;
1526 #size-cells = <0>;
1529 pcs5: ethernet-phy@0 {
1535 compatible = "fsl,fman-memac-mdio";
1537 little-endian;
1538 #address-cells = <1>;
1539 #size-cells = <0>;
1542 pcs6: ethernet-phy@0 {
1548 compatible = "fsl,fman-memac-mdio";
1550 little-endian;
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1555 pcs7: ethernet-phy@0 {
1561 compatible = "fsl,fman-memac-mdio";
1563 little-endian;
1564 #address-cells = <1>;
1565 #size-cells = <0>;
1568 pcs8: ethernet-phy@0 {
1574 compatible = "fsl,fman-memac-mdio";
1576 little-endian;
1577 #address-cells = <1>;
1578 #size-cells = <0>;
1581 pcs9: ethernet-phy@0 {
1587 compatible = "fsl,fman-memac-mdio";
1589 little-endian;
1590 #address-cells = <1>;
1591 #size-cells = <0>;
1594 pcs10: ethernet-phy@0 {
1600 compatible = "fsl,fman-memac-mdio";
1602 little-endian;
1603 #address-cells = <1>;
1604 #size-cells = <0>;
1607 pcs11: ethernet-phy@0 {
1613 compatible = "fsl,fman-memac-mdio";
1615 little-endian;
1616 #address-cells = <1>;
1617 #size-cells = <0>;
1620 pcs12: ethernet-phy@0 {
1626 compatible = "fsl,fman-memac-mdio";
1628 little-endian;
1629 #address-cells = <1>;
1630 #size-cells = <0>;
1633 pcs13: ethernet-phy@0 {
1639 compatible = "fsl,fman-memac-mdio";
1641 little-endian;
1642 #address-cells = <1>;
1643 #size-cells = <0>;
1646 pcs14: ethernet-phy@0 {
1652 compatible = "fsl,fman-memac-mdio";
1654 little-endian;
1655 #address-cells = <1>;
1656 #size-cells = <0>;
1659 pcs15: ethernet-phy@0 {
1665 compatible = "fsl,fman-memac-mdio";
1667 little-endian;
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1672 pcs16: ethernet-phy@0 {
1678 compatible = "fsl,fman-memac-mdio";
1680 little-endian;
1681 #address-cells = <1>;
1682 #size-cells = <0>;
1685 pcs17: ethernet-phy@0 {
1691 compatible = "fsl,fman-memac-mdio";
1693 little-endian;
1694 #address-cells = <1>;
1695 #size-cells = <0>;
1698 pcs18: ethernet-phy@0 {
1704 compatible = "pinctrl-single";
1706 #address-cells = <1>;
1707 #size-cells = <0>;
1708 pinctrl-single,bit-per-mux;
1709 pinctrl-single,register-width = <32>;
1710 pinctrl-single,function-mask = <0x7>;
1712 i2c1_scl: i2c1-scl-pins {
1713 pinctrl-single,bits = <0x0 0 0x7>;
1716 i2c1_scl_gpio: i2c1-scl-gpio-pins {
1717 pinctrl-single,bits = <0x0 0x1 0x7>;
1720 i2c2_scl: i2c2-scl-pins {
1721 pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
1724 i2c2_scl_gpio: i2c2-scl-gpio-pins {
1725 pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
1728 i2c3_scl: i2c3-scl-pins {
1729 pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
1732 i2c3_scl_gpio: i2c3-scl-gpio-pins {
1733 pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
1736 i2c4_scl: i2c4-scl-pins {
1737 pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
1740 i2c4_scl_gpio: i2c4-scl-gpio-pins {
1741 pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
1744 i2c5_scl: i2c5-scl-pins {
1745 pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
1748 i2c5_scl_gpio: i2c5-scl-gpio-pins {
1749 pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
1752 i2c6_scl: i2c6-scl-pins {
1753 pinctrl-single,bits = <0x4 0x2 0x7>;
1756 i2c6_scl_gpio: i2c6-scl-gpio-pins {
1757 pinctrl-single,bits = <0x4 0x1 0x7>;
1760 i2c7_scl: i2c7-scl-pins {
1761 pinctrl-single,bits = <0x4 0x2 0x7>;
1764 i2c7_scl_gpio: i2c7-scl-gpio-pins {
1765 pinctrl-single,bits = <0x4 0x1 0x7>;
1768 i2c0_scl: i2c0-scl-pins {
1769 pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
1772 i2c0_scl_gpio: i2c0-scl-gpio-pins {
1773 pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
1777 fsl_mc: fsl-mc@80c000000 {
1778 compatible = "fsl,qoriq-mc";
1781 msi-parent = <&its 0>;
1782 /* iommu-map property is fixed up by u-boot */
1783 iommu-map = <0 &smmu 0 0>;
1784 dma-coherent;
1785 #address-cells = <3>;
1786 #size-cells = <1>;
1789 * Region type 0x0 - MC portals
1790 * Region type 0x1 - QBMAN portals
1799 #address-cells = <1>;
1800 #size-cells = <0>;
1803 compatible = "fsl,qoriq-mc-dpmac";
1805 pcs-handle = <&pcs1>;
1809 compatible = "fsl,qoriq-mc-dpmac";
1811 pcs-handle = <&pcs2>;
1815 compatible = "fsl,qoriq-mc-dpmac";
1817 pcs-handle = <&pcs3>;
1821 compatible = "fsl,qoriq-mc-dpmac";
1823 pcs-handle = <&pcs4>;
1827 compatible = "fsl,qoriq-mc-dpmac";
1829 pcs-handle = <&pcs5>;
1833 compatible = "fsl,qoriq-mc-dpmac";
1835 pcs-handle = <&pcs6>;
1839 compatible = "fsl,qoriq-mc-dpmac";
1841 pcs-handle = <&pcs7>;
1845 compatible = "fsl,qoriq-mc-dpmac";
1847 pcs-handle = <&pcs8>;
1851 compatible = "fsl,qoriq-mc-dpmac";
1853 pcs-handle = <&pcs9>;
1857 compatible = "fsl,qoriq-mc-dpmac";
1859 pcs-handle = <&pcs10>;
1863 compatible = "fsl,qoriq-mc-dpmac";
1865 pcs-handle = <&pcs11>;
1869 compatible = "fsl,qoriq-mc-dpmac";
1871 pcs-handle = <&pcs12>;
1875 compatible = "fsl,qoriq-mc-dpmac";
1877 pcs-handle = <&pcs13>;
1881 compatible = "fsl,qoriq-mc-dpmac";
1883 pcs-handle = <&pcs14>;
1887 compatible = "fsl,qoriq-mc-dpmac";
1889 pcs-handle = <&pcs15>;
1893 compatible = "fsl,qoriq-mc-dpmac";
1895 pcs-handle = <&pcs16>;
1899 compatible = "fsl,qoriq-mc-dpmac";
1901 pcs-handle = <&pcs17>;
1905 compatible = "fsl,qoriq-mc-dpmac";
1907 pcs-handle = <&pcs18>;
1915 compatible = "linaro,optee-tz";