Lines Matching +full:ls1088a +full:- +full:pcie
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Freescale Layerscape SoCs
26 #include "pcie-designware.h"
31 #define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
46 #define PEXPME(idx) BIT(31 - (idx) * 4)
72 #define ls_pcie_pf_lut_readl_addr(addr) ls_pcie_pf_lut_readl(pcie, addr)
73 #define to_ls_pcie(x) dev_get_drvdata((x)->dev)
75 static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
77 struct dw_pcie *pci = pcie->pci;
80 header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
86 /* Clear multi-function bit */
87 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
89 struct dw_pcie *pci = pcie->pci;
91 iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
95 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
98 struct dw_pcie *pci = pcie->pci;
100 val = ioread32(pci->dbi_base + PCIE_STRFMR1);
102 iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
105 /* Forward error response of outbound non-posted requests */
106 static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
108 struct dw_pcie *pci = pcie->pci;
110 iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
113 static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off)
115 if (pcie->big_endian)
116 return ioread32be(pcie->pf_lut_base + off);
118 return ioread32(pcie->pf_lut_base + off);
121 static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val)
123 if (pcie->big_endian)
124 iowrite32be(val, pcie->pf_lut_base + off);
126 iowrite32(val, pcie->pf_lut_base + off);
132 struct ls_pcie *pcie = to_ls_pcie(pci);
136 val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);
138 ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);
145 dev_err(pcie->pci->dev, "PME_Turn_off timeout\n");
151 struct ls_pcie *pcie = to_ls_pcie(pci);
159 val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);
161 ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);
172 dev_err(pcie->pci->dev, "L2 exit timeout\n");
180 struct ls_pcie *pcie = to_ls_pcie(pci);
182 ls_pcie_fix_error_response(pcie);
185 ls_pcie_clear_multifunction(pcie);
188 ls_pcie_drop_msg_tlp(pcie);
214 struct ls_pcie *pcie = to_ls_pcie(pci);
216 scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF);
231 struct ls_pcie *pcie = to_ls_pcie(pci);
233 return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index));
239 struct ls_pcie *pcie = to_ls_pcie(pci);
241 scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMECR, PEXPME(pcie->index));
247 struct ls_pcie *pcie = to_ls_pcie(pci);
256 val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
258 ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
260 val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
262 ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
264 val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
266 ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
268 val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
270 ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
313 { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata },
314 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata },
315 { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata },
316 { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata },
317 { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata },
318 { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata },
319 { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },
320 { .compatible = "fsl,ls2088a-pcie", .data = &layerscape_drvdata },
321 { .compatible = "fsl,ls1088a-pcie", .data = &layerscape_drvdata },
327 struct device *dev = &pdev->dev;
329 struct ls_pcie *pcie;
333 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
334 if (!pcie)
335 return -ENOMEM;
339 return -ENOMEM;
341 pcie->drvdata = of_device_get_match_data(dev);
343 pci->dev = dev;
344 pcie->pci = pci;
345 pci->pp.ops = pcie->drvdata->ops;
348 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
349 if (IS_ERR(pci->dbi_base))
350 return PTR_ERR(pci->dbi_base);
352 pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian");
354 pcie->pf_lut_base = pci->dbi_base + pcie->drvdata->pf_lut_off;
356 if (pcie->drvdata->scfg_support) {
357 pcie->scfg =
358 syscon_regmap_lookup_by_phandle_args(dev->of_node,
359 "fsl,pcie-scfg", 1,
361 if (IS_ERR(pcie->scfg)) {
363 return PTR_ERR(pcie->scfg);
366 pcie->index = index[1];
369 if (!ls_pcie_is_bridge(pcie))
370 return -ENODEV;
372 platform_set_drvdata(pdev, pcie);
374 return dw_pcie_host_init(&pci->pp);
379 struct ls_pcie *pcie = dev_get_drvdata(dev);
381 if (!pcie->drvdata->pm_support)
384 return dw_pcie_suspend_noirq(pcie->pci);
389 struct ls_pcie *pcie = dev_get_drvdata(dev);
392 if (!pcie->drvdata->pm_support)
395 ret = pcie->drvdata->exit_from_l2(&pcie->pci->pp);
399 return dw_pcie_resume_noirq(pcie->pci);
409 .name = "layerscape-pcie",