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/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
[all …]
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416_ani.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
39 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
41 HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
46 * and related information. This is done for noise and spur
49 * rssi value (e.g. beacon frames from an ap in station mode)
55 * ANI_ENA_RSSI indicates whether rssi-based processing should
56 * done, this is enabled based on operating mode and is meaningful
[all …]
H A Dar5416phy.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
130 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
131 #define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */
132 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
133 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-…
134 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz…
135 #define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_ani.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
35 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
37 HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
42 * and related information. This is done for noise and spur
45 * rssi value (e.g. beacon frames from an ap in station mode)
51 * ANI_ENA_RSSI indicates whether rssi-based processing should
52 * done, this is enabled based on operating mode and is meaningful
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_reset.c121 ahp->ah_hwp = HAL_TRUE_CHIP; in ar9300_attach_hw_platform()
196 * Mask used to construct AAD for CCMP-AES in ar9300_init_mfp()
197 * Cisco spec defined bits 0-3 as mask in ar9300_init_mfp()
226 centers->ctl_center = centers->ext_center = in ar9300_get_channel_centers()
227 centers->synth_center = ichan->channel; in ar9300_get_channel_centers()
234 * In 20/40 phy mode, the center frequency is in ar9300_get_channel_centers()
238 centers->synth_center = ichan->channel + HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers()
241 centers->synth_center = ichan->channel - HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers()
242 extoff = -1; in ar9300_get_channel_centers()
245 centers->ctl_center = in ar9300_get_channel_centers()
[all …]
H A Dar9300.h48 #define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */
51 * Various fifo fill before Tx start, in 64-byte units
55 #define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1)
151 * Per-channel ANI state private to the driver.
178 u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */
195 ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI))
201 u_int32_t ast_ani_spurup; /* ANI increased spur immunity */
202 u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */
206 u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
211 u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
[all …]
H A Dar9300_eeprom.c91 AH9300(ah)->calibration_data_source = source; in ar9300_calibration_data_set()
100 return AH9300(ah)->calibration_data_source; in ar9300_calibration_data_get()
114 AH9300(ah)->calibration_data_source_address = size; in ar9300_calibration_data_address_set()
123 return AH9300(ah)->calibration_data_source_address; in ar9300_calibration_data_address_get()
150 mptr = &ahp->ah_eeprom; in ar9300_eeprom_template_install()
163 return -1; in ar9300_eeprom_template_install()
174 nptr = -1; in ar9300_eeprom_restore_something()
180 AH9300(ah)->calibration_data_source = calibration_data_none; in ar9300_eeprom_restore_something()
181 AH9300(ah)->calibration_data_source_address = 0; in ar9300_eeprom_restore_something()
194 AH9300(ah)->calibration_data_source = calibration_data_none; in ar9300_eeprom_restore_something()
[all …]
/freebsd/sys/dev/ath/ath_hal/
H A Dah.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
26 * structure for use with the device. Hardware-related operations that
67 * error occurs--i.e. you cannot check it for success.
81 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
84 HAL_ESELFTEST = 14, /* Hardware self-test failed */
106 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
112 HAL_CAP_TPC = 16, /* per-packet tx power control */
[all …]
H A Dah_internal.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
38 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */
41 #define howmany(x, y) (((x)+((y)-1))/(y))
45 #define offsetof(type, field) ((size_t)(&((type *)0)->field))
66 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */
67 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */
68 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */
[all …]
/freebsd/share/dict/
H A Dweb2a12 A-b-c book
13 A-b-c method
14 abdomino-uterotomy
15 Abdul-baha
16 a-be
20 able-bodied
21 able-bodiedness
22 able-minded
23 able-mindedness
27 Abor-miri
[all …]
H A Dweb261459 enable
99810 Jean-Christophe
99811 Jean-Pierre
108611 low
117962 mode
187919 spur
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211_reset.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
40 * 16 MHz mode, divider ratio = 198 = NP+S. N=16, S=4 or 6, P=12
50 { 1, 0x46, 96 }, /* 2312 -19 */
51 { 1, 0x46, 97 }, /* 2317 -18 */
52 { 1, 0x46, 98 }, /* 2322 -17 */
53 { 1, 0x46, 99 }, /* 2327 -16 */
54 { 1, 0x46, 100 }, /* 2332 -15 */
[all …]
/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu_subr.c1 /*-
2 * SPDX-License-Identifier: ISC
10 * distributed with the Asus RT-N16 firmware source code release.
41 if (_sc->dev != NULL) \
42 device_printf(_sc->dev, _fmt, ##__VA_ARGS__); \
91 ((uint8_t)BHND_PMU_GET_BITS((_sc)->caps, BHND_PMU_CAP_REV))
94 bhnd_core_clkctl_wait((_sc)->clkctl, (_val), (_mask))
100 CHIPC_CST4330_CHIPMODE_SDIOD((_sc)->io->rd_chipst((_sc)->io_ctx))
113 * @retval non-zero if the query state could not be initialized.
119 query->dev = dev; in bhnd_pmu_query_init()
[all …]
/freebsd/contrib/pam_modules/pam_passwdqc/
H A Dwordset_4k.c6 * I've replaced two 7-character words to save space.
1316 "enable",
2221 "low",
2382 "mode",
3444 "spur",