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Searched +full:lgm +full:- +full:syscon (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/soc/intel/
H A Dintel,lgm-syscon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/intel/intel,lgm-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain(LGM) Syscon
10 - Chuanhua Lei <lchuanhua@maxlinear.com>
11 - Rahul Tanwar <rtanwar@maxlinear.com>
16 - const: intel,lgm-syscon
17 - const: syscon
24 "#address-cells":
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/linux/Documentation/devicetree/bindings/phy/
H A Dintel,lgm-emmc-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain(LGM) eMMC PHY
10 - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
13 Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
16 The eMMC PHY node should be the child of a syscon node with the
19 - compatible: Should be one of the following:
20 "intel,lgm-syscon", "syscon"
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/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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/linux/drivers/phy/intel/
H A Dphy-intel-lgm-emmc.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mfd/syscon.h>
64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
67 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
75 rate = clk_get_rate(priv->emmcclk); in intel_emmc_phy_power()
78 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); in intel_emmc_phy_power()
88 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
91 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
102 ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG, in intel_emmc_phy_power()
106 dev_err(&phy->dev, "caldone failed, ret=%d\n", ret); in intel_emmc_phy_power()
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H A Dphy-intel-lgm-combo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
11 #include <linux/mfd/syscon.h>
20 #include <dt-bindings/phy/phy.h>
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
114 return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid), in intel_cbphy_iphy_enable()
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/linux/drivers/clk/x86/
H A Dclk-lgm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
8 #include <linux/clk-provider.h>
9 #include <linux/mfd/syscon.h>
12 #include <dt-bindings/clock/intel,lgm-clk.h>
13 #include "clk-cgu.h"
121 * It's more efficient to provide an explicit table due to non-linear
427 struct device *dev = &pdev->dev; in lgm_cgu_probe()
428 struct device_node *np = dev->of_node; in lgm_cgu_probe()
434 return -ENOMEM; in lgm_cgu_probe()
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/linux/drivers/leds/blink/
H A Dleds-lgm-sso.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/mfd/syscon.h>
23 #define SSO_DEV_NAME "lgm-sso"
55 #define DATA_CLK_EDGE 0 /* 0-rising, 1-falling */
63 * SW - Software has to update the SWU bit
64 * GPTC - General Purpose timer is used as clock source
65 * FPID - Divided FSC clock (FPID) is used as clock source
149 if (rate <= priv->freq[i]) in sso_get_blink_rate_idx()
153 return -1; in sso_get_blink_rate_idx()
179 return pin - LED_GRP1_PIN_MAX; in sso_led_pin_blink_off()
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/linux/drivers/mmc/host/
H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
92 * On some SoCs the syscon area has a feature where the upper 16-bits of
93 * each 32-bit register act as a write mask for the lower 16-bits. This allows
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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