Lines Matching +full:lgm +full:- +full:syscon
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
92 * On some SoCs the syscon area has a feature where the upper 16-bits of
93 * each 32-bit register act as a write mask for the lower 16-bits. This allows
101 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
103 * @reg: Offset within the syscon of the register containing this field
105 * @shift: Bit offset within @reg of this field (or -1 if not avail)
114 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
119 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
123 * accessible via the syscon API.
133 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
144 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
167 * struct sdhci_arasan_data - Arasan Controller Data
177 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
223 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
229 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
244 reg = readl(host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_set_delaychain()
250 writel(reg, host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_set_delaychain()
257 reg = readl(host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_set_dll()
263 writel(reg, host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_set_dll()
268 return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg, in sdhci_arasan_phy_set_dll()
289 reg = readl(host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_dll_set_freq()
292 writel(reg, host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_dll_set_freq()
296 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
315 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; in sdhci_arasan_syscon_write()
316 u32 reg = fld->reg; in sdhci_arasan_syscon_write()
317 u16 width = fld->width; in sdhci_arasan_syscon_write()
318 s16 shift = fld->shift; in sdhci_arasan_syscon_write()
328 return -EINVAL; in sdhci_arasan_syscon_write()
330 if (sdhci_arasan->soc_ctl_map->hiword_update) in sdhci_arasan_syscon_write()
342 mmc_hostname(host->mmc), ret); in sdhci_arasan_syscon_write()
351 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_set_clock()
354 if (!IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
355 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { in sdhci_arasan_set_clock()
369 sdhci_set_clock(host, host->max_clk); in sdhci_arasan_set_clock()
370 if (phy_power_on(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
372 mmc_hostname(host->mmc)); in sdhci_arasan_set_clock()
376 sdhci_arasan->is_phy_on = true; in sdhci_arasan_set_clock()
393 if (ctrl_phy && sdhci_arasan->is_phy_on) { in sdhci_arasan_set_clock()
394 phy_power_off(sdhci_arasan->phy); in sdhci_arasan_set_clock()
395 sdhci_arasan->is_phy_on = false; in sdhci_arasan_set_clock()
398 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) { in sdhci_arasan_set_clock()
409 if (clk_data->set_clk_delays && clock > PHY_CLK_TOO_SLOW_HZ) in sdhci_arasan_set_clock()
410 clk_data->set_clk_delays(host); in sdhci_arasan_set_clock()
412 if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) { in sdhci_arasan_set_clock()
417 } else if (sdhci_arasan->internal_phy_reg) { in sdhci_arasan_set_clock()
424 if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) in sdhci_arasan_set_clock()
427 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) in sdhci_arasan_set_clock()
438 if (phy_power_on(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
440 mmc_hostname(host->mmc)); in sdhci_arasan_set_clock()
444 sdhci_arasan->is_phy_on = true; in sdhci_arasan_set_clock()
455 if (ios->enhanced_strobe) in sdhci_arasan_hs400_enhanced_strobe()
471 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { in sdhci_arasan_reset()
481 switch (ios->signal_voltage) { in sdhci_arasan_voltage_switch()
497 return -EINVAL; in sdhci_arasan_voltage_switch()
518 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_arasan_cqhci_irq()
568 * sdhci_arasan_suspend - Suspend method for the driver
582 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_arasan_suspend()
583 mmc_retune_needed(host->mmc); in sdhci_arasan_suspend()
585 if (sdhci_arasan->has_cqe) { in sdhci_arasan_suspend()
586 ret = cqhci_suspend(host->mmc); in sdhci_arasan_suspend()
595 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { in sdhci_arasan_suspend()
596 ret = phy_power_off(sdhci_arasan->phy); in sdhci_arasan_suspend()
604 sdhci_arasan->is_phy_on = false; in sdhci_arasan_suspend()
607 clk_disable(pltfm_host->clk); in sdhci_arasan_suspend()
608 clk_disable(sdhci_arasan->clk_ahb); in sdhci_arasan_suspend()
614 * sdhci_arasan_resume - Resume method for the driver
628 ret = clk_enable(sdhci_arasan->clk_ahb); in sdhci_arasan_resume()
634 ret = clk_enable(pltfm_host->clk); in sdhci_arasan_resume()
640 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { in sdhci_arasan_resume()
641 ret = phy_power_on(sdhci_arasan->phy); in sdhci_arasan_resume()
646 sdhci_arasan->is_phy_on = true; in sdhci_arasan_resume()
655 if (sdhci_arasan->has_cqe) in sdhci_arasan_resume()
656 return cqhci_resume(host->mmc); in sdhci_arasan_resume()
666 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
683 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_sdcardclk_recalc_rate()
685 return host->mmc->actual_clock; in sdhci_arasan_sdcardclk_recalc_rate()
693 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
710 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_sampleclk_recalc_rate()
712 return host->mmc->actual_clock; in sdhci_arasan_sampleclk_recalc_rate()
720 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
723 * @degrees: The clock phase shift between 0 - 359.
735 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_sdcardclk_set_phase()
742 if (host->version < SDHCI_SPEC_300) in sdhci_zynqmp_sdcardclk_set_phase()
745 switch (host->timing) { in sdhci_zynqmp_sdcardclk_set_phase()
786 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
789 * @degrees: The clock phase shift between 0 - 359.
801 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_sampleclk_set_phase()
808 if (host->version < SDHCI_SPEC_300) in sdhci_zynqmp_sampleclk_set_phase()
814 switch (host->timing) { in sdhci_zynqmp_sampleclk_set_phase()
852 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
855 * @degrees: The clock phase shift between 0 - 359.
867 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_sdcardclk_set_phase()
871 if (host->version < SDHCI_SPEC_300) in sdhci_versal_sdcardclk_set_phase()
874 switch (host->timing) { in sdhci_versal_sdcardclk_set_phase()
919 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
922 * @degrees: The clock phase shift between 0 - 359.
934 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_sampleclk_set_phase()
938 if (host->version < SDHCI_SPEC_300) in sdhci_versal_sampleclk_set_phase()
941 switch (host->timing) { in sdhci_versal_sampleclk_set_phase()
995 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_net_emmc_sdcardclk_set_phase()
998 switch (host->timing) { in sdhci_versal_net_emmc_sdcardclk_set_phase()
1040 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_net_emmc_sampleclk_set_phase()
1044 switch (host->timing) { in sdhci_versal_net_emmc_sampleclk_set_phase()
1105 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; in arasan_zynqmp_execute_tuning()
1112 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_execute_tuning()
1127 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
1136 * - Many existing devices don't seem to do this and work fine. To keep
1140 * - The value of corecfg_clockmultiplier should sync with that of corresponding
1150 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_clockmultiplier()
1156 /* If we have a map, we expect to have a syscon */ in sdhci_arasan_update_clockmultiplier()
1157 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_clockmultiplier()
1158 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_clockmultiplier()
1159 mmc_hostname(host->mmc)); in sdhci_arasan_update_clockmultiplier()
1163 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); in sdhci_arasan_update_clockmultiplier()
1167 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
1175 * - Many existing devices don't seem to do this and work fine. To keep
1179 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
1188 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_baseclkfreq()
1189 u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000); in sdhci_arasan_update_baseclkfreq()
1195 /* If we have a map, we expect to have a syscon */ in sdhci_arasan_update_baseclkfreq()
1196 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_baseclkfreq()
1197 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_baseclkfreq()
1198 mmc_hostname(host->mmc)); in sdhci_arasan_update_baseclkfreq()
1202 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); in sdhci_arasan_update_baseclkfreq()
1209 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_set_clk_delays()
1211 clk_set_phase(clk_data->sampleclk, in sdhci_arasan_set_clk_delays()
1212 clk_data->clk_phase_in[host->timing]); in sdhci_arasan_set_clk_delays()
1213 clk_set_phase(clk_data->sdcardclk, in sdhci_arasan_set_clk_delays()
1214 clk_data->clk_phase_out[host->timing]); in sdhci_arasan_set_clk_delays()
1221 struct device_node *np = dev->of_node; in arasan_dt_read_clk_phase()
1228 * Tap Values then use the pre-defined values. in arasan_dt_read_clk_phase()
1234 prop, clk_data->clk_phase_in[timing], in arasan_dt_read_clk_phase()
1235 clk_data->clk_phase_out[timing]); in arasan_dt_read_clk_phase()
1240 clk_data->clk_phase_in[timing] = clk_phase[0]; in arasan_dt_read_clk_phase()
1241 clk_data->clk_phase_out[timing] = clk_phase[1]; in arasan_dt_read_clk_phase()
1245 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1263 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; in arasan_dt_parse_clk_phases()
1265 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { in arasan_dt_parse_clk_phases()
1271 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); in arasan_dt_parse_clk_phases()
1278 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1279 clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1283 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) { in arasan_dt_parse_clk_phases()
1290 clk_data->clk_phase_in[i] = versal_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1291 clk_data->clk_phase_out[i] = versal_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1294 if (of_device_is_compatible(dev->of_node, "xlnx,versal-net-emmc")) { in arasan_dt_parse_clk_phases()
1301 clk_data->clk_phase_in[i] = versal_net_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1302 clk_data->clk_phase_out[i] = versal_net_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1306 "clk-phase-legacy"); in arasan_dt_parse_clk_phases()
1308 "clk-phase-mmc-hs"); in arasan_dt_parse_clk_phases()
1310 "clk-phase-sd-hs"); in arasan_dt_parse_clk_phases()
1312 "clk-phase-uhs-sdr12"); in arasan_dt_parse_clk_phases()
1314 "clk-phase-uhs-sdr25"); in arasan_dt_parse_clk_phases()
1316 "clk-phase-uhs-sdr50"); in arasan_dt_parse_clk_phases()
1318 "clk-phase-uhs-sdr104"); in arasan_dt_parse_clk_phases()
1320 "clk-phase-uhs-ddr50"); in arasan_dt_parse_clk_phases()
1322 "clk-phase-mmc-ddr52"); in arasan_dt_parse_clk_phases()
1324 "clk-phase-mmc-hs200"); in arasan_dt_parse_clk_phases()
1326 "clk-phase-mmc-hs400"); in arasan_dt_parse_clk_phases()
1473 /* SoC-specific compatible strings w/ soc_ctl_map */
1475 .compatible = "rockchip,rk3399-sdhci-5.1",
1479 .compatible = "intel,lgm-sdhci-5.1-emmc",
1483 .compatible = "intel,lgm-sdhci-5.1-sdxc",
1487 .compatible = "intel,keembay-sdhci-5.1-emmc",
1491 .compatible = "intel,keembay-sdhci-5.1-sd",
1495 .compatible = "intel,keembay-sdhci-5.1-sdio",
1500 .compatible = "arasan,sdhci-8.9a",
1504 .compatible = "arasan,sdhci-5.1",
1508 .compatible = "arasan,sdhci-4.9a",
1512 .compatible = "xlnx,zynqmp-8.9a",
1516 .compatible = "xlnx,versal-8.9a",
1520 .compatible = "xlnx,versal-net-emmc",
1528 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1545 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_register_sdcardclk()
1546 struct device_node *np = dev->of_node; in sdhci_arasan_register_sdcardclk()
1551 ret = of_property_read_string_index(np, "clock-output-names", 0, in sdhci_arasan_register_sdcardclk()
1554 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); in sdhci_arasan_register_sdcardclk()
1562 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops; in sdhci_arasan_register_sdcardclk()
1564 clk_data->sdcardclk_hw.init = &sdcardclk_init; in sdhci_arasan_register_sdcardclk()
1565 clk_data->sdcardclk = in sdhci_arasan_register_sdcardclk()
1566 devm_clk_register(dev, &clk_data->sdcardclk_hw); in sdhci_arasan_register_sdcardclk()
1567 if (IS_ERR(clk_data->sdcardclk)) in sdhci_arasan_register_sdcardclk()
1568 return PTR_ERR(clk_data->sdcardclk); in sdhci_arasan_register_sdcardclk()
1569 clk_data->sdcardclk_hw.init = NULL; in sdhci_arasan_register_sdcardclk()
1572 clk_data->sdcardclk); in sdhci_arasan_register_sdcardclk()
1580 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1597 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_register_sampleclk()
1598 struct device_node *np = dev->of_node; in sdhci_arasan_register_sampleclk()
1603 ret = of_property_read_string_index(np, "clock-output-names", 1, in sdhci_arasan_register_sampleclk()
1606 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); in sdhci_arasan_register_sampleclk()
1614 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops; in sdhci_arasan_register_sampleclk()
1616 clk_data->sampleclk_hw.init = &sampleclk_init; in sdhci_arasan_register_sampleclk()
1617 clk_data->sampleclk = in sdhci_arasan_register_sampleclk()
1618 devm_clk_register(dev, &clk_data->sampleclk_hw); in sdhci_arasan_register_sampleclk()
1619 if (IS_ERR(clk_data->sampleclk)) in sdhci_arasan_register_sampleclk()
1620 return PTR_ERR(clk_data->sampleclk); in sdhci_arasan_register_sampleclk()
1621 clk_data->sampleclk_hw.init = NULL; in sdhci_arasan_register_sampleclk()
1624 clk_data->sampleclk); in sdhci_arasan_register_sampleclk()
1632 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1641 struct device_node *np = dev->of_node; in sdhci_arasan_unregister_sdclk()
1643 if (!of_property_present(np, "#clock-cells")) in sdhci_arasan_unregister_sdclk()
1646 of_clk_del_provider(dev->of_node); in sdhci_arasan_unregister_sdclk()
1650 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1655 * 0: the Core supports only 32-bit System Address Bus.
1656 * 1: the Core supports 64-bit System Address Bus.
1660 * Keem Bay does not support 64-bit access.
1669 soc_ctl_map = sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_support64b()
1673 /* If we have a map, we expect to have a syscon */ in sdhci_arasan_update_support64b()
1674 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_support64b()
1675 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_support64b()
1676 mmc_hostname(host->mmc)); in sdhci_arasan_update_support64b()
1680 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value); in sdhci_arasan_update_support64b()
1684 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1694 * Note: without seriously re-architecting SDHCI's clock code and testing on
1700 * re-architecting SDHCI if we see some benefit to it.
1708 struct device_node *np = dev->of_node; in sdhci_arasan_register_sdclk()
1713 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0) in sdhci_arasan_register_sdclk()
1735 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_set_dynamic_config()
1736 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; in sdhci_zynqmp_set_dynamic_config()
1759 !!(host->mmc->caps & MMC_CAP_NONREMOVABLE)); in sdhci_zynqmp_set_dynamic_config()
1763 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000); in sdhci_zynqmp_set_dynamic_config()
1778 !!(host->mmc->caps & MMC_CAP_8_BIT_DATA)); in sdhci_zynqmp_set_dynamic_config()
1793 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_add_host()
1798 if (!sdhci_arasan->has_cqe) in sdhci_arasan_add_host()
1805 cq_host = devm_kzalloc(host->mmc->parent, in sdhci_arasan_add_host()
1808 ret = -ENOMEM; in sdhci_arasan_add_host()
1812 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; in sdhci_arasan_add_host()
1813 cq_host->ops = &sdhci_arasan_cqhci_ops; in sdhci_arasan_add_host()
1815 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_arasan_add_host()
1817 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_arasan_add_host()
1819 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_arasan_add_host()
1842 struct device *dev = &pdev->dev; in sdhci_arasan_probe()
1843 struct device_node *np = dev->of_node; in sdhci_arasan_probe()
1849 return -EINVAL; in sdhci_arasan_probe()
1851 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); in sdhci_arasan_probe()
1858 sdhci_arasan->host = host; in sdhci_arasan_probe()
1860 sdhci_arasan->soc_ctl_map = data->soc_ctl_map; in sdhci_arasan_probe()
1861 sdhci_arasan->clk_ops = data->clk_ops; in sdhci_arasan_probe()
1863 node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0); in sdhci_arasan_probe()
1865 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); in sdhci_arasan_probe()
1868 if (IS_ERR(sdhci_arasan->soc_ctl_base)) { in sdhci_arasan_probe()
1870 PTR_ERR(sdhci_arasan->soc_ctl_base), in sdhci_arasan_probe()
1871 "Can't get syscon\n"); in sdhci_arasan_probe()
1878 sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb"); in sdhci_arasan_probe()
1879 if (IS_ERR(sdhci_arasan->clk_ahb)) { in sdhci_arasan_probe()
1880 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb), in sdhci_arasan_probe()
1891 ret = clk_prepare_enable(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
1897 /* If clock-frequency property is set, use the provided value */ in sdhci_arasan_probe()
1898 if (pltfm_host->clock && in sdhci_arasan_probe()
1899 pltfm_host->clock != clk_get_rate(clk_xin)) { in sdhci_arasan_probe()
1900 ret = clk_set_rate(clk_xin, pltfm_host->clock); in sdhci_arasan_probe()
1902 dev_err(&pdev->dev, "Failed to set SD clock rate\n"); in sdhci_arasan_probe()
1919 if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) in sdhci_arasan_probe()
1920 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; in sdhci_arasan_probe()
1922 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) in sdhci_arasan_probe()
1923 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; in sdhci_arasan_probe()
1925 pltfm_host->clk = clk_xin; in sdhci_arasan_probe()
1927 if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1")) in sdhci_arasan_probe()
1930 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") || in sdhci_arasan_probe()
1931 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") || in sdhci_arasan_probe()
1932 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) { in sdhci_arasan_probe()
1936 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in sdhci_arasan_probe()
1945 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { in sdhci_arasan_probe()
1946 host->mmc_host_ops.execute_tuning = in sdhci_arasan_probe()
1949 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN; in sdhci_arasan_probe()
1950 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; in sdhci_arasan_probe()
1953 arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data); in sdhci_arasan_probe()
1955 ret = mmc_of_parse(host->mmc); in sdhci_arasan_probe()
1961 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { in sdhci_arasan_probe()
1970 sdhci_arasan->phy = ERR_PTR(-ENODEV); in sdhci_arasan_probe()
1971 if (of_device_is_compatible(np, "arasan,sdhci-5.1")) { in sdhci_arasan_probe()
1972 sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan"); in sdhci_arasan_probe()
1973 if (IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_probe()
1974 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy), in sdhci_arasan_probe()
1975 "No phy for arasan,sdhci-5.1.\n"); in sdhci_arasan_probe()
1979 ret = phy_init(sdhci_arasan->phy); in sdhci_arasan_probe()
1985 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_arasan_probe()
1987 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_arasan_probe()
1989 sdhci_arasan->has_cqe = true; in sdhci_arasan_probe()
1990 host->mmc->caps2 |= MMC_CAP2_CQE; in sdhci_arasan_probe()
1992 if (!of_property_read_bool(np, "disable-cqe-dcmd")) in sdhci_arasan_probe()
1993 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; in sdhci_arasan_probe()
1996 if (of_device_is_compatible(np, "xlnx,versal-net-emmc")) in sdhci_arasan_probe()
1997 sdhci_arasan->internal_phy_reg = true; in sdhci_arasan_probe()
2006 if (!IS_ERR(sdhci_arasan->phy)) in sdhci_arasan_probe()
2007 phy_exit(sdhci_arasan->phy); in sdhci_arasan_probe()
2013 clk_disable_unprepare(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
2024 struct clk *clk_ahb = sdhci_arasan->clk_ahb; in sdhci_arasan_remove()
2025 struct clk *clk_xin = pltfm_host->clk; in sdhci_arasan_remove()
2027 if (!IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_remove()
2028 if (sdhci_arasan->is_phy_on) in sdhci_arasan_remove()
2029 phy_power_off(sdhci_arasan->phy); in sdhci_arasan_remove()
2030 phy_exit(sdhci_arasan->phy); in sdhci_arasan_remove()
2033 sdhci_arasan_unregister_sdclk(&pdev->dev); in sdhci_arasan_remove()
2043 .name = "sdhci-arasan",