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/linux/drivers/irqchip/
H A Dqcom-pdc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
47 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
79 /* Use previous DRV (client) region and shift to bank 3-4 */ in pdc_x1e_irq_enable_write()
84 /* Use our own region and shift to bank 0-2 */ in pdc_x1e_irq_enable_write()
86 bank -= 2; in pdc_x1e_irq_enable_write()
129 __pdc_enable_intr(d->hwirq, on); in pdc_enable_intr()
151 * Level sensitive active low LOW
152 * Rising edge sensitive NOT USED
153 * Falling edge sensitive LOW
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dsodaville.txt14 - <1st cell>: The interrupt-number that identifies the interrupt source.
15 - <2nd cell>: The level-sense information, encoded as follows:
16 4 - active high level-sensitive
17 8 - active low level-sensitive
23 #gpio-cells = <2>;
24 #interrupt-cells = <2>;
34 interrupt-controller;
35 gpio-controller;
42 * level interrupt
45 interrupt-parent = <&pcigpio>;
H A Dnvidia,tegra20-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
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H A Dsocionext,uniphier-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v5-iwb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
24 - $ref: /schemas/interrupt-controller.yaml#
28 const: arm,gic-v5-iwb
32 - description: IWB control frame
34 "#address-cells":
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H A Dimg,pdc-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/img,pdc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - James Hogan <jhogan@kernel.org>
19 const: img,pdc-intc
24 interrupt-controller: true
26 '#interrupt-cells':
28 <1st-cell>: The interrupt-number that identifies the interrupt source.
29 0-7: Peripheral interrupts
[all …]
H A Dinterrupts.txt5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
45 -----------
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H A Dsnps,archs-idu-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/snps,archs-idu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARC-HS Interrupt Distribution Unit
10 - Vineet Gupta <vgupta@kernel.org>
13 ARC-HS Interrupt Distribution Unit is an optional 2nd level interrupt
22 const: snps,archs-idu-intc
24 interrupt-controller: true
26 '#interrupt-cells':
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H A Darm,gic-v5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
21 - one or more IRS (Interrupt Routing Service)
22 - zero or more ITS (Interrupt Translation Service)
25 - PE-Private Peripheral Interrupts (PPI)
26 - Shared Peripheral Interrupts (SPI)
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/linux/Documentation/virt/kvm/devices/
H A Dxics.rst1 .. SPDX-License-Identifier: GPL-2.0
25 -EINVAL Value greater than KVM_MAX_VCPU_IDS.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
64 bitfields, starting from the least-significant end of the word:
77 * Level sensitive flag, 1 bit
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
[all …]
/linux/arch/arm64/kvm/vgic/
H A Dvgic-v2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/irqchip/arm-gic.h>
31 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2; in vgic_v2_set_underflow()
33 cpuif->vgic_hcr |= GICH_HCR_UIE; in vgic_v2_set_underflow()
44 * - active bit is transferred as is
45 * - pending bit is
46 * - transferred as is in case of edge sensitive IRQs
47 * - set to the line-level (resample time) for level sensitive IRQs
51 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v2_fold_lr_state()
52 struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2; in vgic_v2_fold_lr_state()
[all …]
/linux/Documentation/admin-guide/pm/
H A Dintel_uncore_frequency_scaling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Copyright: |copy| 2022-2023 Intel Corporation
13 ------------
23 Users may have some latency sensitive workloads where they do not want any
30 ---------------
45 This is a read-only attribute. If users adjust max_freq_khz,
50 This is a read-only attribute. If users adjust min_freq_khz,
63 -----------------------------------------------------------------
72 The current sysfs interface supports controls at package and die level.
74 fabric cluster level.
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/linux/Documentation/virt/
H A Dparavirt_ops.rst1 .. SPDX-License-Identifier: GPL-2.0
13 including native machine -- without any hypervisors.
16 corresponding to low-level critical instructions and high-level
18 time by enabling binary patching of the low-level critical operations
23 - simple indirect call
24 These operations correspond to high-level functionality where it is
27 - indirect call which allows optimization with binary patch
28 Usually these operations correspond to low-level critical instructions. They
32 - a set of macros for hand written assembly code
34 because they include sensitive instructions or some code paths in
/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-image-source.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _image-source-controls:
9 The Image Source control class is intended for low-level control of
15 .. _image-source-control-id:
28 same sub-device.
58 The unit cell consists of the whole area of the pixel, sensitive and
59 non-sensitive.
64 .. flat-table:: struct v4l2_area
65 :header-rows: 0
66 :stub-columns: 0
[all …]
/linux/Documentation/security/
H A Dself-protection.rst2 Kernel Self-Protection
5 Kernel self-protection is the design and implementation of systems and
13 In the worst-case scenario, we assume an unprivileged local attacker
15 cases, bugs being exploited will not provide this level of access,
23 The goals for successful self-protection systems would be that they
24 are effective, on by default, require no opt-in by developers, have no
36 from limiting the exposed APIs available to userspace, making in-kernel
41 --------------------------------
47 Executable code and read-only data must not be writable
61 writable, data is not executable, and read-only data is neither writable
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
[all …]
/linux/security/
H A DKconfig.hardening1 # SPDX-License-Identifier: GPL-2.0-only
7 def_bool $(cc-option,-ftrivial-auto-var-init=pattern)
10 def_bool $(cc-optio
[all...]
/linux/Documentation/scheduler/
H A Dsched-nice-design.rst6 nice-levels implementation in the new Linux scheduler.
12 scheduler, (otherwise we'd have done it long ago) because nice level
19 rule so that nice +19 level would be _exactly_ 1 jiffy. To better
34 -*----------------------------------*-----> [nice level]
35 -20 | +19
52 right minimal granularity - and this translates to 5% CPU utilization.
53 But the fundamental HZ-sensitive property for nice+19 still remained,
56 too _strong_ :-)
59 within the constraints of HZ and jiffies and their nasty design level
63 about Linux's nice level support was its asymmetry around the origin
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap4-var-som-om44.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012 Variscite Ltd. - https://www.variscite.com
7 #include "omap4-mcpdm.dtsi"
10 model = "Variscite VAR-SOM-OM44";
11 compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
19 compatible = "ti,abe-twl6040";
20 ti,model = "VAR-SOM-OM44";
22 ti,mclk-freq = <38400000>;
27 ti,audio-routing =
36 compatible = "usb-nop-xceiv";
[all …]
/linux/tools/testing/selftests/kvm/arm64/
H A Dvgic_irq.c1 // SPDX-License-Identifier: GPL-2.0
3 * vgic_irq.c - Test userspace injection of IRQs
29 bool level_sensitive; /* 1 is level, 0 is edge */
36 * 0x00 (highest priority) - 0xF8 (lowest priority), in steps of 8
44 #define LOWEST_PRIO (KVM_NUM_PRIOS - 1)
46 #define IRQ_DEFAULT_PRIO (LOWEST_PRIO - 1)
68 int level; member
74 uint32_t num, int level, boo
192 kvm_inject_call(kvm_inject_cmd cmd,uint32_t first_intid,uint32_t num,int level,bool expect_failure) kvm_inject_call() argument
239 guest_set_irq_line(uint32_t intid,uint32_t level) guest_set_irq_line() argument
509 kvm_irq_line_check(struct kvm_vm * vm,uint32_t intid,int level,struct test_args * test_args,bool expect_failure) kvm_irq_line_check() argument
528 kvm_irq_set_level_info_check(int gic_fd,uint32_t intid,int level,bool expect_failure) kvm_irq_set_level_info_check() argument
655 int level = inject_args->level; run_guest_cmd() local
[all...]
/linux/arch/powerpc/kvm/
H A Dbook3s_xics.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 * We use a two-level tree to store interrupt source information.
19 #define KVMPPC_XICS_SRC_MASK (KVMPPC_XICS_IRQ_PER_ICS - 1)
44 u8 lsi; /* level-sensitive interrupt */
122 if (vcpu->arch.icp && nr == vcpu->arch.icp->server_num) in kvmppc_xics_find_server()
123 return vcpu->arch.icp; in kvmppc_xics_find_server()
139 ics = xics->ics[icsid]; in kvmppc_xics_find_ics()
/linux/Documentation/power/
H A Dswsusp.rst47 - If you feel ACPI works pretty well on your system, you might try::
51 - If you would like to write hibernation image to swap and then suspend
56 - If you have SATA disks, you'll need recent kernels with SATA suspend
58 are built into kernel -- not modules. [There's way to make
68 - The resume process checks for the presence of the resume device,
72 - The resume process may be triggered in two ways:
81 read-only) otherwise data may be corrupted.
87 Last revised: 2003-10-20 by Pavel Machek
90 -------------------------
163 between 0-640KB. That way, I'd have to make sure that 0-640KB is free
[all …]
/linux/tools/perf/scripts/python/
H A Dexported-sql-viewer.py2 # SPDX-License-Identifier: GPL-2.0
3 # exported-sql-viewer.py: view data from sql database
4 # Copyright (c) 2014-2018, Intel Corporation.
7 # export-to-sqlite.py or the export-to-postgresql.py script. Refer to those
11 # call-graph can be displayed for the pt_example database like this:
13 # python tools/perf/scripts/python/exported-sql-viewer.py pt_example
18 # python tools/perf/scripts/python/exported-sql-viewer.py "hostname=myhost username=myuser password…
20 # The result is a GUI window with a tree representing a context-sensitive
21 # call-graph. Expanding a couple of levels of the tree and adjusting column
26 # v- ls
[all …]
/linux/arch/x86/kvm/
H A Di8259.c4 * Copyright (c) 2003-2004 Fabrice Bellard
44 static void pic_irq_request(struct kvm *kvm, int level);
47 __acquires(&s->lock) in pic_lock()
49 spin_lock(&s->lock); in pic_lock()
53 __releases(&s->lock) in pic_unlock()
55 bool wakeup = s->wakeup_needed; in pic_unlock()
59 s->wakeup_needed = false; in pic_unlock()
61 spin_unlock(&s->lock); in pic_unlock()
64 kvm_for_each_vcpu(i, vcpu, s->kvm) { in pic_unlock()
76 s->isr &= ~(1 << irq); in pic_clear_isr()
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-platform-dfl-port1 What: /sys/bus/platform/devices/dfl-port.0/id
5 Description: Read-only. It returns id of this port. One DFL FPGA device
9 What: /sys/bus/platform/devices/dfl-port.0/afu_id
13 Description: Read-only. User can program different PR bitstreams to FPGA
18 What: /sys/bus/platform/devices/dfl-port.0/power_state
22 Description: Read-only. It reports the APx (AFU Power) state, different APx
23 means different throttling level. When reading this file, it
24 returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6.
26 What: /sys/bus/platform/devices/dfl-port.0/ap1_event
30 Description: Read-write. Read this file for AP1 (AFU Power State 1) event.
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