| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
[all …]
|
| H A D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
|
| H A D | open-pic.txt | 13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
42 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
|
| H A D | nxp,lpc3220-mic.txt | 4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
[all …]
|
| H A D | interrupts.txt | 5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
45 -----------
[all …]
|
| H A D | amazon,al-fic.txt | 5 - compatible: should be "amazon,al-fic"
6 - reg: physical base address and size of the registers
7 - interrupt-controller: identifies the node as an interrupt controller
8 - #interrupt-cells : must be 2. Specifies the number of cells needed to encode
9 an interrupt source. Supported trigger types are low-to-high edge
10 triggered and active high level-sensitive.
11 - interrupts: describes which input line in the interrupt parent, this
20 amazon_fic: interrupt-controller@fd8a8500 {
21 compatible = "amazon,al-fic";
22 interrupt-controller;
[all …]
|
| /linux/drivers/irqchip/ |
| H A D | qcom-pdc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
47 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
79 /* Use previous DRV (client) region and shift to bank 3-4 */ in pdc_x1e_irq_enable_write()
84 /* Use our own region and shift to bank 0-2 */ in pdc_x1e_irq_enable_write()
86 bank -= 2; in pdc_x1e_irq_enable_write()
129 __pdc_enable_intr(d->hwirq, on); in pdc_enable_intr()
151 * Level sensitive active low LOW
152 * Rising edge sensitive NOT USED
153 * Falling edge sensitive LOW
[all …]
|
| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | sodaville.txt | 14 - <1st cell>: The interrupt-number that identifies the interrupt source.
15 - <2nd cell>: The level-sense information, encoded as follows:
16 4 - active high level-sensitive
17 8 - active low level-sensitive
23 #gpio-cells = <2>;
24 #interrupt-cells = <2>;
34 interrupt-controller;
35 gpio-controller;
42 * level interrupt
45 interrupt-parent = <&pcigpio>;
|
| H A D | nvidia,tegra20-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
[all …]
|
| H A D | socionext,uniphier-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
[all …]
|
| H A D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
53 controller, are both extremely non-linear. The header file
54 <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
65 module and the sets-of-ports as "controllers".
69 one of the interrupt signals generated by a set-of-ports. The intent is
[all …]
|
| H A D | cdns,gpio.txt | 4 - compatible: should be "cdns,gpio-r1p02".
5 - reg: the register base address and size.
6 - #gpio-cells: should be 2.
9 <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
11 - gpio-controller: marks the device as a GPIO controller.
12 - clocks: should contain one entry referencing the peripheral clock driving
16 - ngpios: integer number of gpio lines supported by this controller, up to 32.
17 - interrupts: interrupt specifier for the controllers interrupt.
18 - interrupt-controller: marks the device as an interrupt controller. When
19 defined, interrupts, interrupt-parent and #interrupt-cells
[all …]
|
| /linux/Documentation/virt/kvm/devices/ |
| H A D | xics.rst | 1 .. SPDX-License-Identifier: GPL-2.0
25 -EINVAL Value greater than KVM_MAX_VCPU_IDS.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
64 bitfields, starting from the least-significant end of the word:
77 * Level sensitive flag, 1 bit
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
[all …]
|
| /linux/arch/arm64/kvm/vgic/ |
| H A D | vgic-v2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/irqchip/arm-gic.h>
31 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2; in vgic_v2_set_underflow()
33 cpuif->vgic_hcr |= GICH_HCR_UIE; in vgic_v2_set_underflow()
44 * - active bit is transferred as is
45 * - pending bit is
46 * - transferred as is in case of edge sensitive IRQs
47 * - set to the line-level (resample time) for level sensitive IRQs
51 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v2_fold_lr_state()
52 struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2; in vgic_v2_fold_lr_state()
[all …]
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | brcm,bcm2835-gpio.txt | 7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
|
| /linux/Documentation/admin-guide/pm/ |
| H A D | intel_uncore_frequency_scaling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 :Copyright: |copy| 2022-2023 Intel Corporation
13 ------------
23 Users may have some latency sensitive workloads where they do not want any
30 ---------------
45 This is a read-only attribute. If users adjust max_freq_khz,
50 This is a read-only attribute. If users adjust min_freq_khz,
63 -----------------------------------------------------------------
72 The current sysfs interface supports controls at package and die level.
74 fabric cluster level.
[all …]
|
| /linux/Documentation/virt/ |
| H A D | paravirt_ops.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 including native machine -- without any hypervisors.
16 corresponding to low-level critical instructions and high-level
18 time by enabling binary patching of the low-level critical operations
23 - simple indirect call
24 These operations correspond to high-level functionality where it is
27 - indirect call which allows optimization with binary patch
28 Usually these operations correspond to low-level critical instructions. They
32 - a set of macros for hand written assembly code
34 because they include sensitive instructions or some code paths in
|
| /linux/security/ |
| H A D | Kconfig.hardening | 1 # SPDX-License-Identifier: GPL-2.0-only
12 flaws, this plugin is available to identify and zero-initialize
13 such variables, depending on the chosen level of coverage.
23 def_bool $(cc-option,-ftrivial-auto-var-init=pattern)
26 def_bool $(cc-option,-ftrivial-auto-var-init=zero)
29 # Clang 16 and later warn about using the -enable flag, but it
31 …def_bool $(cc-option,-ftrivial-auto-var-init=zero -enable-trivial-auto-var-init-zero-knowing-it-wi…
51 This chooses the level of coverage over classes of potentially
64 bool "zero-init structs marked for userspace (weak)"
69 Zero-initialize any structures on the stack containing
[all …]
|
| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | ext-ctrls-image-source.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _image-source-controls:
9 The Image Source control class is intended for low-level control of
15 .. _image-source-control-id:
28 same sub-device.
58 The unit cell consists of the whole area of the pixel, sensitive and
59 non-sensitive.
64 .. flat-table:: struct v4l2_area
65 :header-rows: 0
66 :stub-columns: 0
[all …]
|
| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpic.txt | 14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
47 - pic-no-reset
53 configuration registers to a sane state-- masked or
60 - big-endian
[all …]
|
| /linux/drivers/media/pci/tw5864/ |
| H A D | tw5864-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
[all …]
|
| /linux/Documentation/security/ |
| H A D | self-protection.rst | 2 Kernel Self-Protection
5 Kernel self-protection is the design and implementation of systems and
13 In the worst-case scenario, we assume an unprivileged local attacker
15 cases, bugs being exploited will not provide this level of access,
23 The goals for successful self-protection systems would be that they
24 are effective, on by default, require no opt-in by developers, have no
36 from limiting the exposed APIs available to userspace, making in-kernel
41 --------------------------------
47 Executable code and read-only data must not be writable
61 writable, data is not executable, and read-only data is neither writable
[all …]
|
| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap4-var-som-om44.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012 Variscite Ltd. - https://www.variscite.com
7 #include "omap4-mcpdm.dtsi"
10 model = "Variscite VAR-SOM-OM44";
11 compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
19 compatible = "ti,abe-twl6040";
20 ti,model = "VAR-SOM-OM44";
22 ti,mclk-freq = <38400000>;
27 ti,audio-routing =
36 compatible = "usb-nop-xceiv";
[all …]
|
| /linux/Documentation/scheduler/ |
| H A D | sched-nice-design.rst | 6 nice-levels implementation in the new Linux scheduler.
12 scheduler, (otherwise we'd have done it long ago) because nice level
19 rule so that nice +19 level would be _exactly_ 1 jiffy. To better
34 -*----------------------------------*-----> [nice level]
35 -20 | +19
52 right minimal granularity - and this translates to 5% CPU utilization.
53 But the fundamental HZ-sensitive property for nice+19 still remained,
56 too _strong_ :-)
59 within the constraints of HZ and jiffies and their nasty design level
63 about Linux's nice level support was its asymmetry around the origin
[all …]
|
| /linux/tools/testing/selftests/kvm/aarch64/ |
| H A D | vgic_irq.c | |