4  * Copyright (c) 2003-2004 Fabrice Bellard
44 static void pic_irq_request(struct kvm *kvm, int level);
47 	__acquires(&s->lock)  in pic_lock()
49 	spin_lock(&s->lock);  in pic_lock()
53 	__releases(&s->lock)  in pic_unlock()
55 	bool wakeup = s->wakeup_needed;  in pic_unlock()
59 	s->wakeup_needed = false;  in pic_unlock()
61 	spin_unlock(&s->lock);  in pic_unlock()
64 		kvm_for_each_vcpu(i, vcpu, s->kvm) {  in pic_unlock()
76 	s->isr &= ~(1 << irq);  in pic_clear_isr()
77 	if (s != &s->pics_state->pics[0])  in pic_clear_isr()
85 	pic_unlock(s->pics_state);  in pic_clear_isr()
86 	kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);  in pic_clear_isr()
87 	pic_lock(s->pics_state);  in pic_clear_isr()
91  * set irq level. If an edge is detected, then the IRR is set to 1
93 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)  in pic_set_irq1()  argument
97 	if (s->elcr & mask)	/* level triggered */  in pic_set_irq1()
98 		if (level) {  in pic_set_irq1()
99 			ret = !(s->irr & mask);  in pic_set_irq1()
100 			s->irr |= mask;  in pic_set_irq1()
101 			s->last_irr |= mask;  in pic_set_irq1()
103 			s->irr &= ~mask;  in pic_set_irq1()
104 			s->last_irr &= ~mask;  in pic_set_irq1()
107 		if (level) {  in pic_set_irq1()
108 			if ((s->last_irr & mask) == 0) {  in pic_set_irq1()
109 				ret = !(s->irr & mask);  in pic_set_irq1()
110 				s->irr |= mask;  in pic_set_irq1()
112 			s->last_irr |= mask;  in pic_set_irq1()
114 			s->last_irr &= ~mask;  in pic_set_irq1()
116 	return (s->imr & mask) ? -1 : ret;  in pic_set_irq1()
129 	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)  in get_priority()
135  * return the pic wanted interrupt. return -1 if none
141 	mask = s->irr & ~s->imr;  in pic_get_irq()
144 		return -1;  in pic_get_irq()
150 	mask = s->isr;  in pic_get_irq()
151 	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])  in pic_get_irq()
158 		return (priority + s->priority_add) & 7;  in pic_get_irq()
160 		return -1;  in pic_get_irq()
171 	irq2 = pic_get_irq(&s->pics[1]);  in pic_update_irq()
176 		pic_set_irq1(&s->pics[0], 2, 1);  in pic_update_irq()
177 		pic_set_irq1(&s->pics[0], 2, 0);  in pic_update_irq()
179 	irq = pic_get_irq(&s->pics[0]);  in pic_update_irq()
180 	pic_irq_request(s->kvm, irq >= 0);  in pic_update_irq()
191 		    int irq_source_id, int level, bool line_status)  in kvm_pic_set_irq()  argument
193 	struct kvm_pic *s = kvm->arch.vpic;  in kvm_pic_set_irq()
194 	int irq = e->irqchip.pin;  in kvm_pic_set_irq()
200 	irq_level = __kvm_irq_line_state(&s->irq_states[irq],  in kvm_pic_set_irq()
201 					 irq_source_id, level);  in kvm_pic_set_irq()
202 	ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, irq_level);  in kvm_pic_set_irq()
204 	trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,  in kvm_pic_set_irq()
205 			      s->pics[irq >> 3].imr, ret == 0);  in kvm_pic_set_irq()
216 	s->isr |= 1 << irq;  in pic_intack()
218 	 * We don't clear a level sensitive interrupt here  in pic_intack()
220 	if (!(s->elcr & (1 << irq)))  in pic_intack()
221 		s->irr &= ~(1 << irq);  in pic_intack()
223 	if (s->auto_eoi) {  in pic_intack()
224 		if (s->rotate_on_auto_eoi)  in pic_intack()
225 			s->priority_add = (irq + 1) & 7;  in pic_intack()
234 	struct kvm_pic *s = kvm->arch.vpic;  in kvm_pic_read_irq()
236 	s->output = 0;  in kvm_pic_read_irq()
239 	irq = pic_get_irq(&s->pics[0]);  in kvm_pic_read_irq()
241 		pic_intack(&s->pics[0], irq);  in kvm_pic_read_irq()
243 			irq2 = pic_get_irq(&s->pics[1]);  in kvm_pic_read_irq()
245 				pic_intack(&s->pics[1], irq2);  in kvm_pic_read_irq()
251 			intno = s->pics[1].irq_base + irq2;  in kvm_pic_read_irq()
253 			intno = s->pics[0].irq_base + irq;  in kvm_pic_read_irq()
259 		intno = s->pics[0].irq_base + irq;  in kvm_pic_read_irq()
272 	u8 edge_irr = s->irr & ~s->elcr;  in kvm_pic_reset()
275 	s->last_irr = 0;  in kvm_pic_reset()
276 	s->irr &= s->elcr;  in kvm_pic_reset()
277 	s->imr = 0;  in kvm_pic_reset()
278 	s->priority_add = 0;  in kvm_pic_reset()
279 	s->special_mask = 0;  in kvm_pic_reset()
280 	s->read_reg_select = 0;  in kvm_pic_reset()
281 	if (!s->init4) {  in kvm_pic_reset()
282 		s->special_fully_nested_mode = 0;  in kvm_pic_reset()
283 		s->auto_eoi = 0;  in kvm_pic_reset()
285 	s->init_state = 1;  in kvm_pic_reset()
287 	kvm_for_each_vcpu(i, vcpu, s->pics_state->kvm)  in kvm_pic_reset()
310 			s->init4 = val & 1;  in pic_ioport_write()
315 						"level sensitive irq not supported");  in pic_ioport_write()
319 				s->poll = 1;  in pic_ioport_write()
321 				s->read_reg_select = val & 1;  in pic_ioport_write()
323 				s->special_mask = (val >> 5) & 1;  in pic_ioport_write()
329 				s->rotate_on_auto_eoi = cmd >> 2;  in pic_ioport_write()
333 				priority = get_priority(s, s->isr);  in pic_ioport_write()
335 					irq = (priority + s->priority_add) & 7;  in pic_ioport_write()
337 						s->priority_add = (irq + 1) & 7;  in pic_ioport_write()
339 					pic_update_irq(s->pics_state);  in pic_ioport_write()
345 				pic_update_irq(s->pics_state);  in pic_ioport_write()
348 				s->priority_add = (val + 1) & 7;  in pic_ioport_write()
349 				pic_update_irq(s->pics_state);  in pic_ioport_write()
353 				s->priority_add = (irq + 1) & 7;  in pic_ioport_write()
355 				pic_update_irq(s->pics_state);  in pic_ioport_write()
362 		switch (s->init_state) {  in pic_ioport_write()
364 			u8 imr_diff = s->imr ^ val,  in pic_ioport_write()
365 				off = (s == &s->pics_state->pics[0]) ? 0 : 8;  in pic_ioport_write()
366 			s->imr = val;  in pic_ioport_write()
370 						s->pics_state->kvm,  in pic_ioport_write()
373 						!!(s->imr & (1 << irq)));  in pic_ioport_write()
374 			pic_update_irq(s->pics_state);  in pic_ioport_write()
378 			s->irq_base = val & 0xf8;  in pic_ioport_write()
379 			s->init_state = 2;  in pic_ioport_write()
382 			if (s->init4)  in pic_ioport_write()
383 				s->init_state = 3;  in pic_ioport_write()
385 				s->init_state = 0;  in pic_ioport_write()
388 			s->special_fully_nested_mode = (val >> 4) & 1;  in pic_ioport_write()
389 			s->auto_eoi = (val >> 1) & 1;  in pic_ioport_write()
390 			s->init_state = 0;  in pic_ioport_write()
402 			s->pics_state->pics[0].isr &= ~(1 << 2);  in pic_poll_read()
403 			s->pics_state->pics[0].irr &= ~(1 << 2);  in pic_poll_read()
405 		s->irr &= ~(1 << ret);  in pic_poll_read()
408 			pic_update_irq(s->pics_state);  in pic_poll_read()
414 		pic_update_irq(s->pics_state);  in pic_poll_read()
425 	if (s->poll) {  in pic_ioport_read()
427 		s->poll = 0;  in pic_ioport_read()
430 			if (s->read_reg_select)  in pic_ioport_read()
431 				ret = s->isr;  in pic_ioport_read()
433 				ret = s->irr;  in pic_ioport_read()
435 			ret = s->imr;  in pic_ioport_read()
442 	s->elcr = val & s->elcr_mask;  in elcr_ioport_write()
448 	return s->elcr;  in elcr_ioport_read()
464 		pic_ioport_write(&s->pics[0], addr, data);  in picdev_write()
470 		pic_ioport_write(&s->pics[1], addr, data);  in picdev_write()
476 		elcr_ioport_write(&s->pics[addr & 1], data);  in picdev_write()
480 		return -EOPNOTSUPP;  in picdev_write()
501 		*data = pic_ioport_read(&s->pics[addr >> 7], addr);  in picdev_read()
507 		*data = elcr_ioport_read(&s->pics[addr & 1]);  in picdev_read()
511 		return -EOPNOTSUPP;  in picdev_read()
561 static void pic_irq_request(struct kvm *kvm, int level)  in pic_irq_request()  argument
563 	struct kvm_pic *s = kvm->arch.vpic;  in pic_irq_request()
565 	if (!s->output && level)  in pic_irq_request()
566 		s->wakeup_needed = true;  in pic_irq_request()
567 	s->output = level;  in pic_irq_request()
592 		return -ENOMEM;  in kvm_pic_init()
593 	spin_lock_init(&s->lock);  in kvm_pic_init()
594 	s->kvm = kvm;  in kvm_pic_init()
595 	s->pics[0].elcr_mask = 0xf8;  in kvm_pic_init()
596 	s->pics[1].elcr_mask = 0xde;  in kvm_pic_init()
597 	s->pics[0].pics_state = s;  in kvm_pic_init()
598 	s->pics[1].pics_state = s;  in kvm_pic_init()
603 	kvm_iodevice_init(&s->dev_master, &picdev_master_ops);  in kvm_pic_init()
604 	kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);  in kvm_pic_init()
605 	kvm_iodevice_init(&s->dev_elcr, &picdev_elcr_ops);  in kvm_pic_init()
606 	mutex_lock(&kvm->slots_lock);  in kvm_pic_init()
608 				      &s->dev_master);  in kvm_pic_init()
612 	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);  in kvm_pic_init()
616 	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_elcr);  in kvm_pic_init()
620 	mutex_unlock(&kvm->slots_lock);  in kvm_pic_init()
622 	kvm->arch.vpic = s;  in kvm_pic_init()
627 	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);  in kvm_pic_init()
630 	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);  in kvm_pic_init()
633 	mutex_unlock(&kvm->slots_lock);  in kvm_pic_init()
642 	struct kvm_pic *vpic = kvm->arch.vpic;  in kvm_pic_destroy()
647 	mutex_lock(&kvm->slots_lock);  in kvm_pic_destroy()
648 	kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_master);  in kvm_pic_destroy()
649 	kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_slave);  in kvm_pic_destroy()
650 	kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_elcr);  in kvm_pic_destroy()
651 	mutex_unlock(&kvm->slots_lock);  in kvm_pic_destroy()
653 	kvm->arch.vpic = NULL;  in kvm_pic_destroy()