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/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
25 In version 3 of the controller, each layer has fixed memory offset and address
32 - xylon,logicvc-3.02.a-display
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_backend.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
14 #include <linux/dma-mapping.h>
36 /* backend <-> TCON muxing selection done in backend */
39 /* alpha at the lowest z position is not always supported */
56 regmap_write(engine->reg in sun4i_backend_apply_color_correction()
84 sun4i_backend_layer_enable(struct sun4i_backend * backend,int layer,bool enable) sun4i_backend_layer_enable() argument
100 sun4i_backend_drm_format_to_layer(u32 format,u32 * mode) sun4i_backend_drm_format_to_layer() argument
172 sun4i_backend_update_layer_coord(struct sun4i_backend * backend,int layer,struct drm_plane * plane) sun4i_backend_update_layer_coord() argument
196 sun4i_backend_update_yuv_format(struct sun4i_backend * backend,int layer,struct drm_plane * plane) sun4i_backend_update_yuv_format() argument
253 sun4i_backend_update_layer_formats(struct sun4i_backend * backend,int layer,struct drm_plane * plane) sun4i_backend_update_layer_formats() argument
290 sun4i_backend_update_layer_frontend(struct sun4i_backend * backend,int layer,uint32_t fmt) sun4i_backend_update_layer_frontend() argument
329 sun4i_backend_update_layer_buffer(struct sun4i_backend * backend,int layer,struct drm_plane * plane) sun4i_backend_update_layer_buffer() argument
366 sun4i_backend_update_layer_zpos(struct sun4i_backend * backend,int layer,struct drm_plane * plane) sun4i_backend_update_layer_zpos() argument
386 sun4i_backend_cleanup_layer(struct sun4i_backend * backend,int layer) sun4i_backend_cleanup_layer() argument
410 struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane); sun4i_backend_plane_uses_frontend() local
641 sun4i_backend_mode_set(struct sunxi_engine * engine,const struct drm_display_mode * mode) sun4i_backend_mode_set() argument
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/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_layer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
41 * What we call depth in this driver only counts color components, not alpha.
64 .alpha = true,
86 struct drm_device *drm_dev = drm_plane->dev; in logicvc_plane_atomic_check()
87 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_check() local
96 if (!new_state->crtc) in logicvc_plane_atomic_check()
99 crtc_state = drm_atomic_get_new_crtc_state(new_state->stat in logicvc_plane_atomic_check()
140 struct logicvc_layer *layer = logicvc_layer(drm_plane); logicvc_plane_atomic_update() local
146 struct drm_display_mode *mode = &drm_crtc->state->adjusted_mode; logicvc_plane_atomic_update() local
194 u32 alpha; logicvc_plane_atomic_update() local
237 struct logicvc_layer *layer = logicvc_layer(drm_plane); logicvc_plane_atomic_disable() local
260 logicvc_layer_buffer_find_setup(struct logicvc_drm * logicvc,struct logicvc_layer * layer,struct drm_plane_state * state,struct logicvc_layer_buffer_setup * setup) logicvc_layer_buffer_find_setup() argument
353 logicvc_layer_formats_lookup(struct logicvc_layer * layer) logicvc_layer_formats_lookup() argument
355 bool alpha; logicvc_layer_formats_lookup() local
383 logicvc_layer_config_parse(struct logicvc_drm * logicvc,struct logicvc_layer * layer) logicvc_layer_config_parse() argument
435 struct logicvc_layer *layer; logicvc_layer_get_from_index() local
447 struct logicvc_layer *layer; logicvc_layer_get_from_type() local
466 struct logicvc_layer *layer = NULL; logicvc_layer_init() local
558 logicvc_layer_fini(struct logicvc_drm * logicvc,struct logicvc_layer * layer) logicvc_layer_fini() argument
569 struct logicvc_layer *layer; logicvc_layers_attach_crtc() local
586 struct logicvc_layer *layer; logicvc_layers_init() local
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H A Dlogicvc_of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
14 { "lvds-4bits", LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS },
15 { "lvds-3bits", LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS },
33 { "layer", LOGICVC_LAYER_ALPHA_LAYER },
40 .name = "xylon,display-interface",
48 .name = "xylon,display-colorspace",
56 .name = "xylon,display-depth",
60 .name = "xylon,row-stride",
67 .name = "xylon,background-layer",
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_reg.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Andy Yan <andy.yan@rock-chips.com>
69 DRM_FORMAT_YUV420_8BIT, /* yuv420_8bit non-Linear mode only */
70 DRM_FORMAT_YUV420_10BIT, /* yuv420_10bit non-Linear mode only */
71 DRM_FORMAT_YUYV, /* yuv422_8bit non-Linear mode only*/
72 DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */
77 * RGB: linear mode and afbc
78 * YUV: linear mode and rfbc
79 * rfbc is a rockchip defined non-linear mode, produced by
95 DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
[all …]
/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 #include <linux/dma-mapping.h>
21 #include <linux/media-bus-format.h>
34 * --------
39 * +------------------------------------------------------------+
40 * +--------+ | +----------------+ +-----------+ |
41 * | DPDMA | --->| | --> | Video | Video +-------------+ |
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H A Dzynqmp_kms.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP DisplayPort Subsystem - KMS API
5 * Copyright (C) 2017 - 2021 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
48 return container_of(drm, struct zynqmp_dpsub_drm, dev)->dpsub; in to_zynqmp_dpsub()
51 /* --
81 struct zynqmp_disp_layer *layer = dpsub->layers[plane->index]; zynqmp_dpsub_plane_atomic_disable() local
99 struct zynqmp_disp_layer *layer = dpsub->layers[plane->index]; zynqmp_dpsub_plane_atomic_update() local
154 struct zynqmp_disp_layer *layer = dpsub->layers[i]; zynqmp_dpsub_create_planes() local
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/linux/drivers/gpu/drm/arm/
H A Dmalidp_planes.c1 // SPDX-License-Identifier: GPL-2.0-only
26 /* Layer specific register offsets */
57 * This 4-entry look-up-table is used to determine the full 8-bit alpha valu
456 malidp_calc_mmu_control_value(enum mmu_prefetch_mode mode,u8 readahead,u8 n_planes,u32 pgsize) malidp_calc_mmu_control_value() argument
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/linux/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
10 #include <linux/mfd/atmel-hlcdc.h>
24 * struct atmel_hlcdc_plane_state - Atmel HLCDC Plane state structure.
129 static int atmel_hlcdc_format_to_plane_mode(u32 format, u32 *mode) in atmel_hlcdc_format_to_plane_mode()
133 *mode = ATMEL_HLCDC_C8_MODE; in atmel_hlcdc_format_to_plane_mode()
136 *mode in atmel_hlcdc_format_to_plane_mode()
128 atmel_hlcdc_format_to_plane_mode(u32 format,u32 * mode) atmel_hlcdc_format_to_plane_mode() argument
709 const struct drm_display_mode *mode; atmel_hlcdc_plane_atomic_check() local
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/linux/drivers/video/fbdev/
H A Ds3c-fb.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/video/s3c-fb.c
5 * Copyright 2008-2010 Simtec Electronics
15 #include <linux/dma-mapping.h>
31 * setting of the alpha-blending functions that each window has, so only
35 * output timings and as the control for the output power-down state.
38 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
58 #define VALID_BPP(x) (1 << ((x) - 1))
67 * struct s3c_fb_variant - fb variant information
111 * @has_osd_alpha: Set if can change alpha transparency for a window.
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/linux/Documentation/driver-api/media/drivers/
H A Dcx2341x-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----------------------
12 .. note:: the memory long words are little-endian ('intel format').
21 .. code-block:: none
23 ivtvctl -O min=0x02000000,max=0x020000ff
26 register space :-).
35 .. code-block:: none
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
39 ???-??? MPEG buffer(s)
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/linux/Documentation/gpu/
H A Dkomeda-kms.rst1 .. SPDX-License-Identifier: GPL-2.0
22 Layer section in Overview of D71 like display IPs
23 -----
24 Layer is the first pipeline stage, which prepares the pixel data for the next
30 ------
33 The usage of scaler is very flexible and can be connected to layer output
34 for layer scaling, or connected to compositor and scale the whole display
39 -------------------
46 Writeback Layer (wb_layer)
47 --------------------------
[all …]
/linux/drivers/ata/
H A Dpata_cypress.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_cypress.c - Cypress PATA for new ATA layer
49 * cy82c693_set_piomode - set initial PIO mode data
53 * Called to do the PIO mode setup.
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in cy82c693_set_piomode()
64 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 1) < 0) { in cy82c693_set_piomode()
69 time_16 = clamp_val(t.recover - 1, 0, 15) | in cy82c693_set_piomode()
70 (clamp_val(t.active - 1, 0, 15) << 4); in cy82c693_set_piomode()
71 time_8 = clamp_val(t.act8b - 1, 0, 15) | in cy82c693_set_piomode()
72 (clamp_val(t.rec8b - 1, 0, 15) << 4); in cy82c693_set_piomode()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
10 uses pata-platform driver to enable the relevant driver in the
21 If you want to use an ATA hard disk, ATA tape drive, ATA CD-ROM or
62 <file:Documentation/admin-guide/kernel-parameters.txt>.
76 This option adds support for ATA-related ACPI objects.
107 comment "Controllers with non-SFF native interface"
125 for chipsets / "South Bridges" supporting low-power modes. Such
128 - Partial: The Phy logic is powered but is in a reduced power
131 - Slumber: The Phy logic is powered but is in an even lower power
134 - DevSleep: The Phy logic may be powered down. The exit latency from
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddpp.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
36 * or a layer to be blended with other DPP, or a rectangle associated with a
40 * - graphic color keyer
41 * - graphic cursor compositing
42 * - graphic or video image source to destination scaling
43 * - image sharping
44 * - video format conversion from 4:2:0 or 4:2:2 to 4:4:4
45 * - Color Space Conversion
46 * - Host LUT gamma adjustment
47 * - Colo
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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-codec.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _codec-controls:
25 .. _mpeg-control-id:
28 -----------------
36 .. _v4l2-mpeg-stream-type:
41 enum v4l2_mpeg_stream_type -
42 The MPEG-1, -2 or -4 output stream type. One cannot assume anything
49 .. flat-table::
50 :header-rows: 0
51 :stub-columns: 0
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/linux/drivers/char/mwave/
H A D3780i.h3 * 3780i.h -- declarations for 3780i.c
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 * 10/23/2000 - Alpha Release
62 #define DSP_MsaDataDSISHigh 0x0008 /* MSA data register: d-store word or high byte of i-stor…
63 #define DSP_MsaDataISLow 0x000A /* MSA data register: low word of i-store */
70 unsigned char ConfigMode:1; /* RW: Configuration mode, 0=normal, 1=config mode */
79 unsigned short DiagnosticMode:1; /* RW: Disgnostic mode 0=nromal, 1=diagnostic mode */
112 unsigned char AccessMode:1; /* RW: 16-bit register access method 0=byte, 1=word */
260 * these values are provided as input to the 3780i support layer. At present,
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/linux/include/media/
H A Ddvb_frontend.h4 * The Digital TV Frontend kABI defines a driver-internal interface for
5 * registering low-level, hardware specific driver to a hardware independent
6 * frontend layer.
28 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
61 * struct dvb_frontend_tune_settings - parameters to adjust frontend tuning
78 * struct dvb_tuner_info - Frontend name and min/max ranges/bandwidths
101 * struct analog_parameters - Parameters to tune into an analog/radio channel
105 * @mode: Tuner mode, as defined on enum v4l2_tuner_type
106 * @audmode: Audio mode as defined for the rxsubchans field at videodev2.h,
116 unsigned int mode; member
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/linux/drivers/gpu/drm/exynos/
H A Dexynos_mixer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Seung-Woo Kim <sw0312.kim@samsung.com>
9 * Based on drivers/media/video/s5p-tv/mixer_reg.c
39 #include "regs-mixer.h"
40 #include "regs-vp.h"
48 * Each coefficient is a 10-bi
314 mixer_cfg_gfx_blend(struct mixer_context * ctx,unsigned int win,unsigned int pixel_alpha,unsigned int alpha) mixer_cfg_gfx_blend() argument
341 mixer_cfg_vp_blend(struct mixer_context * ctx,unsigned int alpha) mixer_cfg_vp_blend() argument
428 mixer_cfg_rgb_fmt(struct mixer_context * ctx,struct drm_display_mode * mode) mixer_cfg_rgb_fmt() argument
506 struct drm_display_mode *mode = &ctx->crtc->base.state->adjusted_mode; mixer_commit() local
1048 mixer_mode_valid(struct exynos_drm_crtc * crtc,const struct drm_display_mode * mode) mixer_mode_valid() argument
1074 mixer_mode_fixup(struct exynos_drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode) mixer_mode_fixup() argument
[all...]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_catalog.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
32 * SSPP sub-blocks/features
34 …* @DPU_SSPP_SCALER_QSEED3_COMPATIBLE, QSEED3-compatible alogorithm support (includes QSEED3, QSEE…
37 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
38 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer
68 * MIXER sub-blocks/features
69 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
78 * DSPP sub-blocks
[all …]
/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_pipeline.h1 /* SPDX-License-Identifier: GPL-2.0 */
27 KOMEDA_COMPONENT_WB_LAYER = 7, /* write back layer */
55 /** komeda_component_funcs - component control functions */
117 * bitmask of BIT(component->id) for the supported inputs/outputs,
165 * - Layer: its user always is plane.
166 * - compiz/improc/timing_ctrlr: the user is crtc.
167 * - wb_layer: wb_conn;
168 * - scaler: plane when input is layer, wb_conn if input is compiz.
185 * - active_inputs = changed_active_inputs | unchanged_active_inputs
186 * - affected_inputs = old->active_inputs | new->active_inputs;
[all …]
/linux/drivers/gpu/drm/kmb/
H A Dkmb_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2018-2020 Intel Corporation
28 /* Conversion (yuv->rgb) matrix from myriadx */
31 1024, -352, -731,
33 -179, 125, -22
[all...]
/linux/
H A DCREDITS1 This is at least a partial credits-file of people that have
4 scripts. The fields are: name (N), email (E), web-address
6 snail-mail address (S).
10 ----------
14 D: Alpha systems hacking, IPv6 and other network related stuff
55 D: in-kernel DRM Maintainer
80 E: tim_alpaerts@toyota-motor-europe.com
81 D: 802.2 class II logical link control layer,
84 S: B-2610 Wilrijk-Antwerpen
89 W: http://www-stu.christs.cam.ac.uk/~aia21/
[all …]
/linux/Documentation/sound/designs/
H A Dseq-oss.rst15 What this does - it provides the emulation of the OSS sequencer, access
30 100 regardless of HZ. That is, even on Alpha system, a tick is always
53 However, each MIDI device is exclusive - that is, if a MIDI device
57 * Real-time event processing:
60 ioctl. To switch to real-time mode, send ABSTIME 0 event. The followed
61 events will be processed in real-time without queued. To switch off the
62 real-time mode, send RELTIME 0 event.
74 Run configure script with both sequencer support (``--with-sequencer=yes``)
75 and OSS emulation (``--with-oss=yes``) options. A module ``snd-seq-oss.o``
102 midi 0: [Emu8000 Port-0] ALSA port 65:0
[all …]
/linux/drivers/platform/raspberrypi/vchiq-mmal/
H A Dmmal-parameters.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 /** Camera-specific parameter ID group. */
31 /** Video-specific parameter ID group. */
33 /** Audio-specific parameter ID group. */
35 /** Clock-specific parameter ID group. */
37 /** Miracast-specific parameter ID group. */
268 * Actual mode is controlled by MMAL_PARAMETER_CAPTURE_MODE.
481 /** @ref MMAL_PARAMETER_BOOLEAN_T. Request an I-frame. */
489 /** @ref MMAL_PARAMETER_UINT32_T. Run-time bit rate control */
507 * because image buffers need to be re-pitched.
[all …]

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