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/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
25 In version 3 of the controller, each layer has fixed memory offset and address
32 - xylon,logicvc-3.02.a-display
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_backend.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
14 #include <linux/dma-mapping.h>
35 /* backend <-> TCON muxing selection done in backend */
38 /* alpha at the lowest z position is not always supported */
55 regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG, in sun4i_backend_apply_color_correction()
59 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i), in sun4i_backend_apply_color_correction()
68 regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG, in sun4i_backend_disable_color_correction()
78 regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG, in sun4i_backend_commit()
84 int layer, bool enable) in sun4i_backend_layer_enable() argument
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H A Dsun8i_vi_layer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
28 if (mixer->cfg->is_de3) { in sun8i_vi_layer_update_alpha()
32 (plane->state->alpha >> 8); in sun8i_vi_layer_update_alpha()
34 val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ? in sun8i_vi_layer_update_alpha()
38 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_update_alpha()
42 } else if (mixer->cfg->vi_num == 1) { in sun8i_vi_layer_update_alpha()
43 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_update_alpha()
47 (plane->state->alpha >> 8)); in sun8i_vi_layer_update_alpha()
55 struct drm_plane_state *state = plane->state; in sun8i_vi_layer_update_coord()
56 const struct drm_format_info *format = state->fb->format; in sun8i_vi_layer_update_coord()
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H A Dsun8i_mixer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/dma-mapping.h>
91 /* for DE2 VI layer which ignores alpha */
100 /* for DE2 VI layer which ignores alpha */
109 /* for DE2 VI layer which ignores alpha */
118 /* for DE2 VI layer which ignores alpha */
127 /* for DE2 VI layer which ignores alpha */
136 /* for DE2 VI layer which ignores alpha */
145 /* for DE2 VI layer which ignores alpha */
154 /* for DE2 VI layer which ignores alpha */
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/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_layer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
41 * What we call depth in this driver only counts color components, not alpha.
64 .alpha = true,
86 struct drm_device *drm_dev = drm_plane->dev; in logicvc_plane_atomic_check()
87 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_check() local
96 if (!new_state->crtc) in logicvc_plane_atomic_check()
99 crtc_state = drm_atomic_get_existing_crtc_state(new_state->state, in logicvc_plane_atomic_check()
100 new_state->crtc); in logicvc_plane_atomic_check()
102 return -EINVAL; in logicvc_plane_atomic_check()
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H A Dlogicvc_of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
14 { "lvds-4bits", LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS },
15 { "lvds-3bits", LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS },
33 { "layer", LOGICVC_LAYER_ALPHA_LAYER },
40 .name = "xylon,display-interface",
48 .name = "xylon,display-colorspace",
56 .name = "xylon,display-depth",
60 .name = "xylon,row-stride",
67 .name = "xylon,background-layer",
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmpc.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
30 * that performs blending of multiple planes, using global and per-pixel alpha.
31 * It also performs post-blending color correction operations according to the
36 * supporting "M MPC inputs -> N MPC outputs" flexible composition
39 * - Programmable blending structure to allow software controlled blending and
41 * - Programmable window location of each DPP in active region of display;
42 * - Combining multiple DPP pipes in one active region when a single DPP pipe
44 * - Combining multiple DPP from different SLS with blending;
45 * - Stereo formats from single DPP in top-bottom or side-by-side modes;
46 * - Stereo formats from 2 DPPs;
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H A Ddpp.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
36 * or a layer to be blended with other DPP, or a rectangle associated with a
40 * - graphic color keyer
41 * - graphic cursor compositing
42 * - graphic or video image source to destination scaling
43 * - image sharping
44 * - video format conversion from 4:2:0 or 4:2:2 to 4:4:4
45 * - Color Space Conversion
46 * - Host LUT gamma adjustment
47 * - Color Gamut Remap
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/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 #include <linux/dma-mapping.h>
21 #include <linux/media-bus-format.h>
34 * --------
39 * +------------------------------------------------------------+
40 * +--------+ | +----------------+ +-----------+ |
41 * | DPDMA | --->| | --> | Video | Video +-------------+ |
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H A Dzynqmp_kms.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP DisplayPort Subsystem - KMS API
5 * Copyright (C) 2017 - 2021 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
47 return container_of(drm, struct zynqmp_dpsub_drm, dev)->dpsub; in to_zynqmp_dpsub()
50 /* -----------------------------------------------------------------------------
61 if (!new_plane_state->crtc) in zynqmp_dpsub_plane_atomic_check()
64 crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc); in zynqmp_dpsub_plane_atomic_check()
80 struct zynqmp_dpsub *dpsub = to_zynqmp_dpsub(plane->dev); in zynqmp_dpsub_plane_atomic_disable()
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/linux/drivers/gpu/drm/arm/
H A Dmalidp_planes.c1 // SPDX-License-Identifier: GPL-2.0-only
26 /* Layer specific register offsets */
57 * This 4-entry look-up-table is used to determine the full 8-bit alpha value
58 * for formats with 1- or 2-bit alpha channels.
59 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
60 * opacity for 2-bit formats.
68 /* readahead for partial-frame prefetch */
72 * Replicate what the default ->reset hook does: free the state pointer and
78 struct malidp_plane_state *state = to_malidp_plane_state(plane->state); in malidp_plane_reset()
81 __drm_atomic_helper_plane_destroy_state(&state->base); in malidp_plane_reset()
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/linux/drivers/gpu/drm/stm/
H A Dltdc.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/media-bus-format.h>
46 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
61 #define LAY_OFS (ldev->caps.layer_ofs)
65 #define LTDC_LCR 0x0004 /* Layer Count */
86 /* Layer register offsets */
87 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
88 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
89 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
90 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
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/linux/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
10 #include <linux/mfd/atmel-hlcdc.h>
23 * struct atmel_hlcdc_plane_state - Atmel HLCDC Plane state structure.
128 static int atmel_hlcdc_format_to_plane_mode(u32 format, u32 *mode) in atmel_hlcdc_format_to_plane_mode() argument
132 *mode = ATMEL_HLCDC_C8_MODE; in atmel_hlcdc_format_to_plane_mode()
135 *mode = ATMEL_HLCDC_XRGB4444_MODE; in atmel_hlcdc_format_to_plane_mode()
138 *mode = ATMEL_HLCDC_ARGB4444_MODE; in atmel_hlcdc_format_to_plane_mode()
141 *mode = ATMEL_HLCDC_RGBA4444_MODE; in atmel_hlcdc_format_to_plane_mode()
144 *mode = ATMEL_HLCDC_RGB565_MODE; in atmel_hlcdc_format_to_plane_mode()
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/linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop2.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Author: Andy Yan <andy.yan@rock-chips.com>
12 #include <linux/media-bus-format.h>
36 #include <dt-bindings/soc/rockchip,vop2.h>
45 +----------+ +-------------+ +-----------+
48 +----------+ +-------------+ +---------------+ +-------------+ +-----------+
49 +----------+ +-------------+ |N from 6 layers| | |
50 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+
52 +----------+ +-------------+ +---------------+ +-------------+ | LVDS |
53 +----------+ +-------------+ +-----------+
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/linux/drivers/gpu/drm/sprd/
H A Dsprd_dpu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/dma-buf.h>
70 /* Layer control bits */
130 struct dpu_context *ctx = &dpu->ctx; in dpu_wait_stop_done()
133 if (ctx->stopped) in dpu_wait_stop_done()
136 rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop, in dpu_wait_stop_done()
138 ctx->evt_stop = false; in dpu_wait_stop_done()
140 ctx->stopped = true; in dpu_wait_stop_done()
143 drm_err(dpu->drm, "dpu wait for stop done time out!\n"); in dpu_wait_stop_done()
144 return -ETIMEDOUT; in dpu_wait_stop_done()
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/linux/drivers/video/fbdev/
H A Ds3c-fb.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/video/s3c-fb.c
5 * Copyright 2008-2010 Simtec Electronics
15 #include <linux/dma-mapping.h>
31 * setting of the alpha-blending functions that each window has, so only
35 * output timings and as the control for the output power-down state.
38 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
58 #define VALID_BPP(x) (1 << ((x) - 1))
67 * struct s3c_fb_variant - fb variant information
111 * @has_osd_alpha: Set if can change alpha transparency for a window.
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/linux/Documentation/driver-api/media/drivers/
H A Dcx2341x-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----------------------
12 .. note:: the memory long words are little-endian ('intel format').
21 .. code-block:: none
23 ivtvctl -O min=0x02000000,max=0x020000ff
26 register space :-).
35 .. code-block:: none
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
39 ???-??? MPEG buffer(s)
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_catalog.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
52 * SSPP sub-blocks/features
54 …* @DPU_SSPP_SCALER_QSEED3_COMPATIBLE, QSEED3-compatible alogorithm support (includes QSEED3, QSEE…
57 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
58 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer
60 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
90 * MIXER sub-blocks/features
91 * @DPU_MIXER_LAYER Layer mixer layer blend configuration,
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/linux/Documentation/gpu/
H A Dkomeda-kms.rst1 .. SPDX-License-Identifier: GPL-2.0
22 Layer section in Overview of D71 like display IPs
23 -----
24 Layer is the first pipeline stage, which prepares the pixel data for the next
30 ------
33 The usage of scaler is very flexible and can be connected to layer output
34 for layer scaling, or connected to compositor and scale the whole display
39 -------------------
46 Writeback Layer (wb_layer)
47 --------------------------
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/linux/drivers/ata/
H A Dpata_cypress.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_cypress.c - Cypress PATA for new ATA layer
49 * cy82c693_set_piomode - set initial PIO mode data
53 * Called to do the PIO mode setup.
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in cy82c693_set_piomode()
64 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 1) < 0) { in cy82c693_set_piomode()
69 time_16 = clamp_val(t.recover - 1, 0, 15) | in cy82c693_set_piomode()
70 (clamp_val(t.active - 1, 0, 15) << 4); in cy82c693_set_piomode()
71 time_8 = clamp_val(t.act8b - 1, 0, 15) | in cy82c693_set_piomode()
72 (clamp_val(t.rec8b - 1, 0, 15) << 4); in cy82c693_set_piomode()
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/linux/drivers/media/v4l2-core/
H A Dv4l2-ctrls-defs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2021 Hans Verkuil <hverkuil-cisco@xs4all.nl>
9 #include <media/v4l2-ctrls.h>
26 "MPEG-1/2 Layer I", in v4l2_ctrl_get_menu()
27 "MPEG-1/2 Layer II", in v4l2_ctrl_get_menu()
28 "MPEG-1/2 Layer III", in v4l2_ctrl_get_menu()
29 "MPEG-2/4 AAC", in v4l2_ctrl_get_menu()
30 "AC-3", in v4l2_ctrl_get_menu()
128 "16-bit CRC", in v4l2_ctrl_get_menu()
141 "MPEG-1", in v4l2_ctrl_get_menu()
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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-codec.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _codec-controls:
24 .. _mpeg-control-id:
27 -----------------
35 .. _v4l2-mpeg-stream-type:
40 enum v4l2_mpeg_stream_type -
41 The MPEG-1, -2 or -4 output stream type. One cannot assume anything
48 .. flat-table::
49 :header-rows: 0
50 :stub-columns: 0
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/linux/Documentation/networking/
H A D6pack.rst1 .. SPDX-License-Identifier: GPL-2.0
7 This is the 6pack-mini-HOWTO, written by
11 :Internet: ajk@comnets.uni-bremen.de
12 :AMPR-net: dg3kq@db0pra.ampr.org
25 - The PC is given full control over the radio
35 This kind of real-time control is especially important to supply several
39 - Each packet transferred over the serial line is supplied with a checksum,
41 Received packets that are corrupt are not passed on to the AX.25 layer.
60 db0bm.automation.fh-aachen.de. In the directory /incoming/dg3kq,
99 - In the linux kernel configuration program, select the code maturity level
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H A Darcnet.rst1 .. SPDX-License-Identifier: GPL-2.0
9 See also arcnet-hardware.txt in this directory for jumper-setting
25 ARCnet 0.32 ALPHA first made it into the Linux kernel 1.1.80 - this was
36 If you don't e-mail me about your success/failure soon, I may be forced to
40 If you think so, why not flame me in a quick little e-mail? Please also
44 My e-mail address is: apenwarr@worldvisions.ca
55 The previous release resulted from many months of on-and-off effort from me
58 ARCnet 2.10 ALPHA, Tomasz's all-new-and-improved RFC1051 support has been
63 ---------------------------------
66 Subscribe by sending a message with the BODY "subscribe linux-arcnet YOUR
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/linux/drivers/char/mwave/
H A D3780i.h3 * 3780i.h -- declarations for 3780i.c
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 * 10/23/2000 - Alpha Release
62 #define DSP_MsaDataDSISHigh 0x0008 /* MSA data register: d-store word or high byte of i-stor…
63 #define DSP_MsaDataISLow 0x000A /* MSA data register: low word of i-store */
70 unsigned char ConfigMode:1; /* RW: Configuration mode, 0=normal, 1=config mode */
79 unsigned short DiagnosticMode:1; /* RW: Disgnostic mode 0=nromal, 1=diagnostic mode */
112 unsigned char AccessMode:1; /* RW: 16-bit register access method 0=byte, 1=word */
260 * these values are provided as input to the 3780i support layer. At present,
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