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/linux/Documentation/driver-api/surface_aggregator/clients/
H A Ddtx.rst39 * **Latch:**
55 Latch States
58 The latch mechanism has two major states: *open* and *closed*. In the
62 The latch can additionally be locked and, correspondingly, unlocked, which
66 documentation for the detachment procedure below. By default, the latch is
82 instructions/commands. In case the latch is unlocked, the led will flash
83 green. If the latch has been locked, the led will be solid red
93 - If the latch is unlocked, the EC will open the latch and the clipboard
98 - If the latch is locked, the EC will *not* open the latch, meaning the
111 latch, after which the user can separate clipboard and base.
[all …]
/linux/include/linux/mfd/abx500/
H A Dab8500.h74 /* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
83 /* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
89 /* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
98 /* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
107 /* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
116 /* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
125 /* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
134 /* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
143 /* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
152 /* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-latch.yaml4 $id: http://devicetree.org/schemas/gpio/gpio-latch.yaml#
7 title: GPIO latch controller
43 of number of latches and the number of inputs per latch is derived from
48 const: gpio-latch
53 description: Array of GPIOs to be used to clock a latch
56 description: Array of GPIOs to be used as inputs per latch
59 description: Delay in nanoseconds to wait after the latch inputs have been
80 gpio-latch {
84 compatible = "gpio-latch";
H A Dsprd,gpio-eic.yaml19 controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and
32 The EIC-latch sub-module is used to latch some special power down signals
33 and generate interrupts, since the EIC-latch does not depend on the APB
48 - sprd,sc9860-eic-latch
58 - sprd,ums512-eic-latch
59 - const: sprd,sc9860-eic-latch
H A Dfairchild,74hc595.yaml11 have a rising-edge triggered latch clock (or storage register clock) pin,
15 the 74HC595 sees as a rising edge on the latch clock that results in a
21 latch clock * trigger
/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A Dpmc.json55 "BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
70 "BriefDescription": "Cycles when at least one thread has the run latch set."
80 "BriefDescription": "Cycles when the run latch is set for all threads."
90 "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT4 mode."
105 "BriefDescription": "Processor cycles gated by the run latch."
140 "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
210 "BriefDescription": "PowerPC instruction completed while the run latch is set."
/linux/arch/sh/include/mach-common/mach/
H A Durquell.h60 #define LATCHCR_OFS 0x3000 /* Latch control register */
61 #define LATCUAR_OFS 0x3010 /* Latch upper address register */
62 #define LATCLAR_OFS 0x3012 /* Latch lower address register */
63 #define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */
64 #define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */
/linux/drivers/tty/serial/8250/
H A D8250_uniphier.c21 * - Divisor latch at 9, no divisor latch access bit
30 /* Divisor Latch Register */
110 /* Divisor latch access bit does not exist. */ in uniphier_serial_out()
144 * This hardware does not have the divisor latch access bit.
145 * The divisor latch register exists at different address.
/linux/kernel/time/
H A Dclockevents.c32 static u64 cev_delta2ns(unsigned long latch, struct clock_event_device *evt, in cev_delta2ns() argument
35 u64 clc = (u64) latch << evt->shift; in cev_delta2ns()
44 * not equal latch, we know that the above shift overflowed. in cev_delta2ns()
46 if ((clc >> evt->shift) != (u64)latch) in cev_delta2ns()
59 * than latch by up to (mult - 1) >> shift. For the min_delta in cev_delta2ns()
62 * we would end up with a latch value larger than the upper in cev_delta2ns()
79 * clockevent_delta2ns - Convert a latch value (device ticks) to nanoseconds
80 * @latch: value to convert
83 * Math helper, returns latch value converted to nanoseconds (bound checked)
85 u64 clockevent_delta2ns(unsigned long latch, struct clock_event_device *evt) in clockevent_delta2ns() argument
[all …]
/linux/arch/sh/include/asm/
H A Dsmc37c93x.h67 #define UART_DLL 0x0 /* Divisor Latch (LS) */
68 #define UART_DLM 0x2 /* Divisor Latch (MS) */
88 /* Alias for Divisor Latch Register */
127 #define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
/linux/drivers/gpio/
H A Dgpio-eic-sprd.c68 * debounce EIC, latch EIC, async EIC and sync EIC,
75 * The latch EIC is used to latch some special power down signals and
76 * generate interrupts, since the latch EIC does not depend on the APB clock
114 "eic-debounce", "eic-latch", "eic-async",
486 * The debounce EIC and latch EIC can only support level trigger, so we in sprd_eic_toggle_trigger()
575 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async in sprd_eic_irq_handler()
709 .compatible = "sprd,sc9860-eic-latch",
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A Dpipeline.json269 "BriefDescription": "Cycles run latch is set and core is in SMT2 mode",
275 "BriefDescription": "cycles this threads run latch is set and the core is in SMT4 mode",
276 "PublicDescription": "Cycles run latch is set and core is in SMT4 mode"
281 "BriefDescription": "Cycles run latch is set and core is in ST mode",
/linux/Documentation/devicetree/bindings/clock/
H A Darmada3700-xtal-clock.txt4 reading the gpio latch register.
7 of the GPIO block where the gpio latch is located.
/linux/drivers/clocksource/
H A Dtimer-ixp4xx.c48 u32 latch; member
138 val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK; in ixp4xx_set_periodic()
177 * So make sure the latch is the best value with the two least in ixp4xx_timer_register()
180 tmr->latch = DIV_ROUND_CLOSEST(timer_freq, in ixp4xx_timer_register()
H A Di8253.c48 * jiffies was incremented and the point where we latch the in i8253_read()
52 outb_p(0x00, PIT_MODE); /* latch the count ASAP */ in i8253_read()
56 /* VIA686a test code... reset the latch if count > max + 1 */ in i8253_read()
/linux/drivers/iio/imu/bmi270/
H A Dbmi270_core.c706 bool active_high, bool open_drain, bool latch) in bmi270_int_pin_config() argument
713 FIELD_PREP(BMI270_INT_LATCH_REG_MSK, latch)); in bmi270_int_pin_config()
738 bool open_drain, active_high, latch; in bmi270_trigger_probe() local
761 latch = false; in bmi270_trigger_probe()
765 latch = true; in bmi270_trigger_probe()
769 latch = false; in bmi270_trigger_probe()
773 latch = true; in bmi270_trigger_probe()
785 latch); in bmi270_trigger_probe()
/linux/Documentation/devicetree/bindings/mtd/
H A Dfsl-upm-nand.txt6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
/linux/arch/powerpc/boot/
H A Dns16550.c20 #define UART_DLL 0 /* Out: Divisor Latch Low */
21 #define UART_DLM 1 /* Out: Divisor Latch High */
/linux/drivers/pci/hotplug/
H A Dshpchp_ctrl.c87 ctrl_info(ctrl, "Latch open on Slot(%s)\n", slot_name(p_slot)); in shpchp_handle_switch_change()
97 ctrl_info(ctrl, "Latch close on Slot(%s)\n", slot_name(p_slot)); in shpchp_handle_switch_change()
548 /* Check to see if (latch closed, card present, power off) */ in shpchp_enable_slot()
557 ctrl_info(ctrl, "Latch open on slot(%s)\n", slot_name(p_slot)); in shpchp_enable_slot()
607 /* Check to see if (latch closed, card present, power on) */ in shpchp_disable_slot()
617 ctrl_info(ctrl, "Latch open on slot(%s)\n", slot_name(p_slot)); in shpchp_disable_slot()
/linux/Documentation/w1/slaves/
H A Dw1_ds2413.rst30 Bit 1: PIOA Output Latch State
32 Bit 3: PIOB Output Latch State
/linux/drivers/pcmcia/
H A Dtcic.c532 u_char latch, sstat; in tcic_interrupt() local
550 latch = sstat ^ socket_table[psock].last_sstat; in tcic_interrupt()
556 if (latch == 0) in tcic_interrupt()
558 events = (latch & TCIC_SSTAT_CD) ? SS_DETECT : 0; in tcic_interrupt()
559 events |= (latch & TCIC_SSTAT_WP) ? SS_WRPROT : 0; in tcic_interrupt()
561 events |= (latch & TCIC_SSTAT_LBAT1) ? SS_STSCHG : 0; in tcic_interrupt()
563 events |= (latch & TCIC_SSTAT_RDY) ? SS_READY : 0; in tcic_interrupt()
564 events |= (latch & TCIC_SSTAT_LBAT1) ? SS_BATDEAD : 0; in tcic_interrupt()
565 events |= (latch & TCIC_SSTAT_LBAT2) ? SS_BATWARN : 0; in tcic_interrupt()
/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-mtk-snfi.yaml48 mediatek,rx-latch-latency-ns:
49 description: Data read latch latency, unit is nanoseconds.
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dmaxim,max34408.yaml53 SHTDN Enable Input. CMOS digital input. Connect to GND to clear the latch and
55 delay. Connect to VDD to enable normal latch operation of the SHTDN output.
/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,mux-clock.yaml78 ti,latch-bit:
81 Latch the mux value to HW, only needed if the register
/linux/Documentation/hwmon/
H A Dadm9240.rst178 a 20 ms active low pulse to reset an external Chassis Intrusion latch.
180 Clear the CI latch by writing value 0 to the sysfs intrusion0_alarm file.
200 that alarm bits may be cleared on read, user-space may latch alarms and

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