Lines Matching full:latch
280 /// The desired flow is: phi ---> bump -+-> comparison-in-latch.
289 /// +-> comparison-in-latch (against upper_bound-bump),
296 /// couldn't be identified, or if the value in the latch's comparison
411 MachineBasicBlock *Latch = L->getLoopLatch(); in findInductionRegister() local
413 if (!Header || !Preheader || !Latch || !ExitingBlock) in findInductionRegister()
435 // latch block, and see if is a result of an addition of form "reg+imm", in findInductionRegister()
438 if (Phi->getOperand(i+1).getMBB() != Latch) in findInductionRegister()
609 MachineBasicBlock *Latch = L->getLoopLatch(); in getLoopTripCount() local
614 else if (MBB == Latch) in getLoopTripCount()
631 if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { in getLoopTripCount()
634 bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false); in getLoopTripCount()
637 if (TB == Latch) in getLoopTripCount()
1189 // Is the induction variable bump feeding the latch condition? in convertToHardwareLoop()
1593 MachineBasicBlock *Latch = L->getLoopLatch(); in fixupInductionVariable() local
1596 if (!(Header && Latch && ExitingBlock)) in fixupInductionVariable()
1609 // %1 = PHI ..., [ latch, %2 ] in fixupInductionVariable()
1619 if (Phi->getOperand(i+1).getMBB() != Latch) in fixupInductionVariable()
1649 if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { in fixupInductionVariable()
1652 bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false); in fixupInductionVariable()
1656 // Since latch is not the exiting block, the latch branch should be an in fixupInductionVariable()
1658 if (TB == Latch) in fixupInductionVariable()
1665 // The latch/exit block does not go back to the header. in fixupInductionVariable()
1671 // This case can happen when the Latch has two jumps like this: in fixupInductionVariable()
1839 MachineBasicBlock *Latch = L->getLoopLatch(); in createPreheaderForLoop() local
1849 if (!Latch || !ExitingBlock || Header->hasAddressTaken()) in createPreheaderForLoop()
1876 // the loop latch. Any additional predecessors of the header should in createPreheaderForLoop()
1893 // Copy all non-latch operands of a header's PHI node to the newly in createPreheaderForLoop()
1899 if (PredB == Latch) in createPreheaderForLoop()
1912 if (PredB != Latch) { in createPreheaderForLoop()
1923 // The header has only two predecessors, but the non-latch predecessor in createPreheaderForLoop()
1933 if (MO.getMBB() != Latch) in createPreheaderForLoop()
1948 if (PB != Latch) { in createPreheaderForLoop()
1959 // It can happen that the latch block will fall through into the header. in createPreheaderForLoop()
1962 bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false); in createPreheaderForLoop()
1966 TII->insertBranch(*Latch, Header, nullptr, EmptyCond, DL); in createPreheaderForLoop()