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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dcache.json105 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
108 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
111 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
114 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
117 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
120 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
123 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
126 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
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/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dmetrics.json89 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
96 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
103 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
110 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
117 …level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
124 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
131 …level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
138 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
145 …ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives a…
152 …"BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per …
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/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A Dmetrics.json14 …"MetricExpr": "(100 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (STALL_SLOT / (CPU_CYCLES * 8)))) + ((…
60 …"MetricExpr": "(100 * ((STALL_SLOT_FRONTEND / (CPU_CYCLES * 8)) - ((BR_MIS_PRED * 4) / CPU_CYCLES)…
100 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
107 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
114 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
121 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
128 …level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
135 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
142 …level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
149 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A Dcache.json111 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
114 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
117 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
120 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
123 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
126 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
147 …"PublicDescription": "Level 3 cache write streaming mode. This event counts for each cycle where t…
150 …"BriefDescription": "Level 3 cache write streaming mode. This event counts for each cycle where th…
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/linux/kernel/rcu/
H A Dtree.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Read-Copy Update mechanism for mutual exclusion (tree-based version)
4 * Internal non-public definitions.
39 * Definition for node within the RCU grace-period-detection hierarchy.
45 unsigned long gp_seq; /* Track rsp->gp_seq. */
56 /* Per-G
82 u8 level; /* root is at level 0. */ global() member
342 struct rcu_node *level[RCU_NUM_LVLS + 1]; global() member
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/linux/drivers/gpu/drm/xe/
H A Dxe_pt.c1 // SPDX-License-Identifier: MIT
6 #include <linux/dma-fence-array.h>
30 /** @children: Array of page-table child nodes */
32 /** @staging: Array of page-table staging nodes */
37 #define xe_pt_set_addr(__xe_pt, __addr) ((__xe_pt)->addr = (__addr))
38 #define xe_pt_addr(__xe_pt) ((__xe_pt)->addr)
47 #define XE_PT_HIGHEST_LEVEL (ARRAY_SIZE(xe_normal_pt_shifts) - 1)
57 return container_of(pt_dir->staging[index], struct xe_pt, base); in xe_pt_entry_staging()
61 unsigned int level) in __xe_pt_empty_pte() argument
64 u16 pat_index = xe->pat.idx[XE_CACHE_WB]; in __xe_pt_empty_pte()
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H A Dxe_pt_walk.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * DOC: GPU page-table tree walking.
9 * The utilities in this file are similar to the CPU page-table walk
11 * the various levels of a page-table tree with an unsigned integer rather
12 * than by name. 0 is the lowest level, and page-tables with level 0 can
14 * can. The user of the utilities determines the highest level.
17 * Each struct xe_ptw, regardless of level is referred to as a page table, and
20 * levels. A shared page table for a given address range is a page-table which
24 * Please keep this code generic so that it can used as a drm-wide page-
27 static u64 xe_pt_addr_end(u64 addr, u64 end, unsigned int level, in xe_pt_addr_end() argument
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/linux/Documentation/admin-guide/mm/
H A Dnumaperf.rst21 +------------------+ +------------------+
22 | Compute Node 0 +-----+ Compute Node 1 |
24 +--------+---------+ +--------+---------+
26 +--------+---------+ +--------+---------+
28 +------------------+ +--------+---------+
36 performance when accessing a given memory target. Each initiator-target
48 # symlinks -v /sys/devices/system/node/nodeX/access0/targets/
49 relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
51 # symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
52 relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
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/linux/drivers/net/wireless/ath/ath5k/
H A Dani.c33 * - "noise immunity"
35 * - "spur immunity"
37 * - "firstep level"
39 * - "OFDM weak signal detection"
41 * - "CCK weak signal detection"
61 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level
63 * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL
66 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_noise_immunity_level() argument
70 * and ath9k use only the last two levels, making this in ath5k_ani_set_noise_immunity_level()
75 static const s8 lo[] = { -52, -56, -60, -64, -70 }; in ath5k_ani_set_noise_immunity_level()
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/linux/Documentation/arch/arm/
H A Dcluster-pm-race-avoidance.rst2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
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/linux/drivers/md/bcache/
H A Dbtree.c1 // SPDX-License-Identifier: GPL-2.0
21 * All configuration is done via sysfs; see Documentation/admin-guide/bcache.rst.
99 (((k)->ptr[0] >> c->bucket_bits) | PTR_GEN(k, 0))
103 #define insert_lock(s, b) ((b)->level <= (s)->lock)
108 return ((void *) btree_bset_first(b)) + b->written * block_bytes(b->c->cache); in write_block()
114 if (b->level && b->keys.nsets) in bch_btree_init_next()
115 bch_btree_sort(&b->keys, &b->c->sort); in bch_btree_init_next()
117 bch_btree_sort_lazy(&b->keys, &b->c->sort); in bch_btree_init_next()
119 if (b->written < btree_blocks(b)) in bch_btree_init_next()
120 bch_bset_init_next(&b->keys, write_block(b), in bch_btree_init_next()
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/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
21 …e data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on thi…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 … Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Las…
31 "Unit": "CPU-M-CF",
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/linux/drivers/staging/vc04_services/bcm2835-camera/
H A Dbcm2835-camera.h1 /* SPDX-License-Identifier: GPL-2.0 */
81 /* H264 level */
83 /* JPEG Q-factor */
92 /* Sequence number of last buffer */
102 /* last frame completion */
120 #define v4l2_dump_pix_format(level, debug, dev, pix_fmt, desc) \ argument
122 v4l2_dbg(level, debug, dev, \
125 (pix_fmt)->width, (pix_fmt)->height, (pix_fmt)->field, \
126 (pix_fmt)->pixelformat, (pix_fmt)->bytesperline, \
127 (pix_fmt)->sizeimage, (pix_fmt)->colorspace, (pix_fmt)->priv); \
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/linux/drivers/usb/serial/
H A Dio_16654.h1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
72 #define FCR_TX_LEVEL_MASK 0x30 // Mask for Tx FIFO Level
73 #define FCR_TX_LEVEL_8 0x00 // Tx FIFO Level = 8 bytes
74 #define FCR_TX_LEVEL_16 0x10 // Tx FIFO Level = 16 bytes
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/linux/fs/xfs/libxfs/
H A Dxfs_btree.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2002,2005 Silicon Graphics, Inc.
49 __be32 magic = ops->buf_ops->magic[idx]; in xfs_btree_magic()
51 /* Ensure we asked for crc for crc-only magics. */ in xfs_btree_magic()
63 * on x86-64. Yes, gcc-11 fails to inline them, and explicit inlining of these
128 int level, in __xfs_btree_check_lblock_hdr() argument
131 struct xfs_mount *mp = cur->bc_mp; in __xfs_btree_check_lblock_hdr()
134 if (!uuid_equal(&block->bb_u.l.bb_uuid, &mp->m_sb.sb_meta_uuid)) in __xfs_btree_check_lblock_hdr()
136 if (block->bb_u.l.bb_blkno != in __xfs_btree_check_lblock_hdr()
139 if (block->bb_u.l.bb_pad != cpu_to_be32(0)) in __xfs_btree_check_lblock_hdr()
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H A Dxfs_btree.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2000-2001,2005 Silicon Graphics, Inc.
28 * The in-core btree key. Overlapping btrees actually store two keys
52 * This nonsense is to make -wlint happy.
74 #define XFS_BB_ALL_BITS ((1u << XFS_BB_NUM_BITS) - 1)
76 #define XFS_BB_ALL_BITS_CRC ((1u << XFS_BB_NUM_BITS_CRC) - 1)
82 XFS_STATS_INC_OFF((cur)->bc_mp, \
83 (cur)->bc_ops->statoff + __XBTS_ ## stat)
85 XFS_STATS_ADD_OFF((cur)->bc_mp, \
86 (cur)->bc_ops->statoff + __XBTS_ ## stat, val)
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/linux/include/uapi/linux/
H A Dhyperv.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
66 VSS_OP_COUNT /* Number of operations, must be last */
95 * driver accesses. However, FREEZE messages from Hyper-V contain
102 * auto-recovery, it should not receive such messages.
171 * Maximum value size - used for both key names and value data, and includes
182 * Note: This value is used in defining the KVP exchange message - this value
193 * Maximum key size - the registry limit for the length of an entry name
203 * implementing the host/guest protocol. 2) A user level daemon that is
228 * data gathering functionality in a user mode daemon. The user level daemon
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/linux/tools/perf/tests/shell/lib/
H A Dperf_metric_validation_rules.json67 …ccesses includes memory reads from last level cache (LLC) addressed to local DRAM and memory reads…
148 "Description": "Sum of TMA level 1 metrics should be 100%",
175 "Description": "Sum of the level 2 children should equal level 1 parent",
198 "Description": "Sum of the level 2 children should equal level 1 parent",
221 "Description": "Sum of the level 2 children should equal level 1 parent",
244 "Description": "Sum of the level 2 children should equal level 1 parent",
285 "Formula": "a-b",
304 "Formula": "a-b",
323 "Formula": "a-b",
/linux/arch/x86/kvm/mmu/
H A Dtdp_mmu.c1 // SPDX-License-Identifier: GPL-2.0
17 INIT_LIST_HEAD(&kvm->arch.tdp_mmu_roots); in kvm_mmu_init_tdp_mmu()
18 spin_lock_init(&kvm->arch.tdp_mmu_pages_lock); in kvm_mmu_init_tdp_mmu()
26 lockdep_assert_held_read(&kvm->mmu_lock); in kvm_lockdep_assert_mmu_lock_held()
28 lockdep_assert_held_write(&kvm->mmu_lock); in kvm_lockdep_assert_mmu_lock_held()
44 KVM_MMU_WARN_ON(atomic64_read(&kvm->arch.tdp_mmu_pages)); in kvm_mmu_uninit_tdp_mmu()
46 WARN_ON(!list_empty(&kvm->arch.tdp_mmu_roots)); in kvm_mmu_uninit_tdp_mmu()
50 * can run before the VM is torn down. Putting the last reference to in kvm_mmu_uninit_tdp_mmu()
58 free_page((unsigned long)sp->external_spt); in tdp_mmu_free_sp()
59 free_page((unsigned long)sp->spt); in tdp_mmu_free_sp()
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/linux/drivers/gpio/
H A Dgpio-max730x.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * - DIN must be stable at the rising edge of clock.
12 * - when writing:
13 * - always clock in 16 clocks at once
14 * - at DIN: D15 first, D0 last
15 * - D0..D7 = databyte, D8..D14 = commandbyte
16 * - D15 = low -> write command
17 * - when reading
18 * - always clock in 16 clocks at once
19 * - at DIN: D15 first, D0 last
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/linux/fs/ext4/
H A Dindirect.c1 // SPDX-License-Identifier: GPL-2.0
11 * Laboratoire MASI - Institut Blaise Pascal
20 * Goal-directed block allocation by Stephen Tweedie
39 p->key = *(p->p = v); in add_chain()
40 p->bh = bh; in add_chain()
44 * ext4_block_to_path - parse the block number into array of offsets
48 * @boundary: set this non-zero if the referred-to block is likely to be
52 * for UNIX filesystems - tree of pointers anchored in the inode, with
54 * This function translates the block number into path in that tree -
61 * inode->i_sb).
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/linux/lib/zlib_inflate/
H A Dinffast.c1 /* inffast.c -- fast decoding
2 * Copyright (C) 1995-2004 Mark Adler
33 available, an end-of-block is encountered, or a data error is encountered.
40 state->mode == LEN
41 strm->avail_in >= 6
42 strm->avail_out >= 258
43 start >= strm->avail_out
44 state->bits < 8
46 On return, state->mode is one of:
48 LEN -- ran out of enough output space or enough available input
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/linux/fs/fat/
H A Dmisc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * 22/11/2000 - Fixed fat_date_unix2dos for dates earlier than 01/01/1980
17 * or filesystem is remounted read-only (default behavior).
18 * In case the file system is remounted read-only, it can be made writable
23 struct fat_mount_options *opts = &MSDOS_SB(sb)->options; in __fat_fs_error()
35 if (opts->errors == FAT_ERRORS_PANIC) in __fat_fs_error()
36 panic("FAT-fs (%s): fs panic from previous error\n", sb->s_id); in __fat_fs_error()
37 else if (opts->errors == FAT_ERRORS_RO && !sb_rdonly(sb)) { in __fat_fs_error()
38 sb->s_flags |= SB_RDONLY; in __fat_fs_error()
39 fat_msg(sb, KERN_ERR, "Filesystem has been set read-only"); in __fat_fs_error()
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/linux/include/net/9p/
H A D9p.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * enum p9_debug_flags - bits for mount time debug parameter
25 * @P9_DEBUG_FSC: FS-cache tracing
52 void _p9_debug(enum p9_debug_flags level, const char *func,
54 #define p9_debug(level, fmt, ...) \ argument
55 _p9_debug(level, __func__, fmt, ##__VA_ARGS__)
57 #define p9_debug(level, fmt, ...) \ argument
62 * enum p9_msg_t - 9P message types
82 * @P9_RATTACH: response with top level handle to file hierarchy
112 * See Also: http://plan9.bell-labs.com/sys/man/5/INDEX.html
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/linux/Documentation/devicetree/bindings/perf/
H A Dmarvell-cn10k-tad.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell CN10K LLC-TAD performance monitor
10 - Bhaskara Budiredla <bbudiredla@marvell.com>
13 The Tag-and-Data units (TADs) maintain coherence and contain CN10K
14 shared on-chip last level cache (LLC). The tad pmu measures the
15 performance of last-level cache. Each tad pmu supports up to eight
23 const: marvell,cn10k-tad-pmu
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