| /linux/drivers/phy/freescale/ |
| H A D | phy-fsl-lynx-10g.c | 83 /* Per SerDes lane registers */
85 /* Lane a Protocol Select status register */
86 #define LNaPSSR0(lane) (0x100 + (lane) * 0x20) argument
93 /* Lane a General Control Register */
94 #define LNaGCR0(lane) (0x800 + (lane) * 0x40 + 0x0) argument
114 #define LNaGCR1(lane) (0x800 + (lane) * 0x40 + 0x4) argument
130 #define LNaRECR0(lane) (0x800 + (lane) * 0x40 + 0x10) argument
140 #define LNaTECR0(lane) (0x800 + (lane) * 0x40 + 0x18) argument
149 #define LNaTTLCR0(lane) (0x800 + (lane) * 0x40 + 0x20) argument
150 #define LNaTTLCR1(lane) (0x800 + (lane) * 0x40 + 0x24) argument
[all …]
|
| /linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-a3700-comphy.c | 40 * When accessing common PHY lane registers directly, we need to shift by 1,
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
227 unsigned int lane; member
234 .lane = _lane, \
246 /* lane 0 */
251 /* lane 1 */
256 /* lane 2 */
387 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */
[all …]
|
| H A D | phy-armada38x-comphy.c | 47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
52 * row index = serdes lane,
64 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
66 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
72 conf |= BIT(lane->port); in a38x_set_conf()
74 conf &= ~BIT(lane->port); in a38x_set_conf()
79 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
84 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
85 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
88 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
[all …]
|
| /linux/drivers/net/dsa/b53/ |
| H A D | b53_serdes.c | 42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config() local
[all …]
|
| /linux/drivers/ufs/core/ |
| H A D | ufs-txeq.c | 148 * bit[3:0]: Device TX Logical LANE 0 PreShoot
149 * bit[7:4]: Device TX Logical LANE 1 PreShoot
151 static inline u8 tx_eq_device_preshoot_decode(u64 eq, u8 lane) in tx_eq_device_preshoot_decode() argument
153 return (u8)((eq >> (lane * TX_HS_PRESHOOT_SHIFT)) & TX_EQ_SETTING_MASK); in tx_eq_device_preshoot_decode()
158 * bit[19:16]: Device TX Logical LANE 0 DeEmphasis
159 * bit[23:20]: Device TX Logical LANE 1 DeEmphasis
161 static inline u8 tx_eq_device_deemphasis_decode(u64 eq, u8 lane) in tx_eq_device_deemphasis_decode() argument
163 return (u8)((eq >> (lane * TX_HS_DEEMPHASIS_SHIFT + 16)) & TX_EQ_SETTING_MASK); in tx_eq_device_deemphasis_decode()
168 * bit[35:32]: Host TX Logical LANE 0 PreShoot
169 * bit[39:36]: Host TX Logical LANE 1 PreShoot
[all …]
|
| /linux/drivers/phy/tegra/ |
| H A D | xusb.c | 127 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, in tegra_xusb_lane_parse_dt()
130 struct device *dev = &lane->pad->dev; in tegra_xusb_lane_parse_dt()
138 err = match_string(lane->soc->funcs, lane->soc->num_funcs, function); in tegra_xusb_lane_destroy()
140 dev_err(dev, "invalid function \"%s\" for lane \"%pOFn\"\n", in tegra_xusb_lane_destroy()
145 lane->function = err; in tegra_xusb_lane_destroy()
153 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_xusb_pad_release()
155 lane->pad->ops->remove(lane);
203 struct phy *lane; in tegra_xusb_pad_register()
115 tegra_xusb_lane_parse_dt(struct tegra_xusb_lane * lane,struct device_node * np) tegra_xusb_lane_parse_dt() argument
141 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_xusb_lane_destroy() local
191 struct phy *lane; tegra_xusb_pad_register() local
208 struct tegra_xusb_lane *lane; tegra_xusb_pad_register() local
320 tegra_xusb_lane_program(struct tegra_xusb_lane * lane) tegra_xusb_lane_program() argument
348 struct tegra_xusb_lane *lane; tegra_xusb_pad_program() local
391 tegra_xusb_lane_check(struct tegra_xusb_lane * lane,const char * function) tegra_xusb_lane_check() argument
403 struct tegra_xusb_lane *lane, *hit = ERR_PTR(-ENODEV); tegra_xusb_find_lane() local
426 struct tegra_xusb_lane *lane, *match = ERR_PTR(-ENODEV); tegra_xusb_port_find_lane() local
662 struct tegra_xusb_lane *lane; tegra_xusb_setup_usb_role_switch() local
1397 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_xusb_padctl_enable_phy_sleepwalk() local
1408 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_xusb_padctl_disable_phy_sleepwalk() local
1419 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_xusb_padctl_enable_phy_wake() local
1430 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_xusb_padctl_disable_phy_wake() local
1441 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_xusb_padctl_remote_wake_detected() local
1473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_phy_xusb_utmi_port_reset() local
1485 struct tegra_xusb_lane *lane; tegra_phy_xusb_utmi_pad_power_on() local
1501 struct tegra_xusb_lane *lane; tegra_phy_xusb_utmi_pad_power_down() local
1538 struct tegra_xusb_lane *lane; tegra_xusb_padctl_get_port_number() local
[all...] |
| H A D | xusb-tegra210.c | 447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0); in tegra210_sata_uphy_enable() local
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
722 usb = tegra_xusb_lane_check(lane, "usb3-ss"); in tegra210_sata_uphy_enable()
1058 static int tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra210_usb3_enable_phy_sleepwalk() argument
1061 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_enable_phy_sleepwalk()
[all …]
|
| H A D | xusb-tegra124.c | 292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_exit() local
475 return tegra124_xusb_padctl_disable(lane->pad->padctl); in tegra124_usb2_phy_exit()
[all …]
|
| H A D | xusb.h | 55 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
63 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
75 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
77 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
85 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
87 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
104 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
106 return container_of(lane, struct tegra_xusb_hsic_lane, base); in to_hsic_lane()
114 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
124 to_sata_lane(struct tegra_xusb_lane * lane) to_sata_lane() argument
278 struct tegra_xusb_lane *lane; global() member
[all...] |
| H A D | xusb-tegra186.c | 324 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra186_usb2_lane_remove() argument
326 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra186_usb2_lane_remove()
331 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra186_utmi_enable_phy_sleepwalk() argument
334 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_sleepwalk()
336 unsigned int index = lane->index; in tegra186_utmi_enable_phy_sleepwalk()
480 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane) in tegra186_utmi_disable_phy_sleepwalk() argument
482 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_disable_phy_sleepwalk()
484 unsigned int index = lane->index; in tegra186_utmi_disable_phy_sleepwalk()
528 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane) in tegra186_utmi_enable_phy_wake() argument
530 struct tegra_xusb_padctl *padctl = lane in tegra186_utmi_enable_phy_wake()
553 tegra186_utmi_disable_phy_wake(struct tegra_xusb_lane * lane) tegra186_utmi_disable_phy_wake() argument
578 tegra186_utmi_phy_remote_wake_detected(struct tegra_xusb_lane * lane) tegra186_utmi_phy_remote_wake_detected() argument
688 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_pad_power_on() local
732 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_pad_power_down() local
843 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_phy_set_mode() local
874 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_phy_power_on() local
952 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_phy_init() local
990 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_phy_exit() local
1135 tegra186_usb3_lane_remove(struct tegra_xusb_lane * lane) tegra186_usb3_lane_remove() argument
1142 tegra186_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane * lane,enum usb_device_speed speed) tegra186_usb3_enable_phy_sleepwalk() argument
1168 tegra186_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane * lane) tegra186_usb3_disable_phy_sleepwalk() argument
1191 tegra186_usb3_enable_phy_wake(struct tegra_xusb_lane * lane) tegra186_usb3_enable_phy_wake() argument
1216 tegra186_usb3_disable_phy_wake(struct tegra_xusb_lane * lane) tegra186_usb3_disable_phy_wake() argument
1241 tegra186_usb3_phy_remote_wake_detected(struct tegra_xusb_lane * lane) tegra186_usb3_phy_remote_wake_detected() argument
1288 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_usb3_phy_power_on() local
1357 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_usb3_phy_power_off() local
[all...] |
| /linux/drivers/gpu/drm/i915/display/ |
| H A D | vlv_dpio_phy_regs.h | 19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
156 #define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
163 #define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) argument
170 #define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) argument
177 #define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) argument
181 #define VLV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) argument
184 #define VLV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) argument
290 #define CHV_TX_DW0(ch, lane) _VLV_TX((ch), (lane), 0) argument
291 #define CHV_TX_DW1(ch, lane) _VLV_TX((ch), (lane), 1) argument
292 #define CHV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
[all …]
|
| H A D | bxt_dpio_phy_regs.h | 28 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ argument
29 ((lane) & 1) * 0x80)
30 #define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \ argument
31 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
101 /* BXT PHY common lane registers */
209 #define BXT_PORT_TX_DW2_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
226 #define BXT_PORT_TX_DW3_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
241 #define BXT_PORT_TX_DW4_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
256 #define BXT_PORT_TX_DW5_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
269 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
|
| /linux/drivers/soundwire/ |
| H A D | generic_bandwidth_allocation.c | 20 unsigned int lane; member
52 if (p_rt->lane != t_data->lane) in sdw_compute_slave_ports()
63 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_slave_ports()
158 if (p_rt->lane != params->lane) in sdw_compute_master_ports()
164 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_master_ports()
186 t_data.lane = params->lane; in sdw_compute_master_ports()
201 /* reset hstop for each lane */ in _sdw_compute_port_params()
204 if (params[i].lane != l) in _sdw_compute_port_params()
238 params[i].lane = group->lanes[i]; in sdw_compute_group_params()
263 if (rate == params[i].rate && p_rt->lane == params[i].lane) in sdw_compute_group_params()
[all …]
|
| /linux/drivers/phy/ |
| H A D | phy-xgene.c | 268 /* PHY lane CSR accessing from SDS indirectly */
520 u32 speed[MAX_LANE]; /* Index for override parameter per lane */
658 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
664 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
673 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
678 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
684 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
689 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
691 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
694 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u3 argument
944 int lane; xgene_phy_sata_cfg_lanes() local
1344 xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx * ctx,int lane) xgene_phy_force_lat_summer_cal() argument
1410 xgene_phy_reset_rxd(struct xgene_phy_ctx * ctx,int lane) xgene_phy_reset_rxd() argument
1424 xgene_phy_gen_avg_val(struct xgene_phy_ctx * ctx,int lane) xgene_phy_gen_avg_val() argument
[all...] |
| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | onnn,nb7vpq904m.yaml | 48 An array of physical data lane indexes. Position determines how
51 Lane number represents the following
52 - 0 is RX2 lane
53 - 1 is TX2 lane
54 - 2 is TX1 lane
55 - 3 is RX1 lane
66 - Port A to RX2 lane
67 - Port B to TX2 lane
68 - Port C to TX1 lane
69 - Port D to RX1 lane
[all …]
|
| /linux/sound/soc/tegra/ |
| H A D | tegra186_asrc.c | 107 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
114 asrc->lane[id].int_part); in tegra186_asrc_runtime_resume()
119 asrc->lane[id].frac_part); in tegra186_asrc_runtime_resume()
171 asrc->lane[id].input_thresh); in tegra186_asrc_in_hw_params()
194 asrc->lane[id].output_thresh); in tegra186_asrc_out_hw_params()
204 if (asrc->lane[id].hwcomp_disable) { in tegra186_asrc_out_hw_params()
223 1, asrc->lane[id].ratio_source); in tegra186_asrc_out_hw_params()
225 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) { in tegra186_asrc_out_hw_params()
228 asrc->lane[id].int_part); in tegra186_asrc_out_hw_params()
231 asrc->lane[id].frac_part); in tegra186_asrc_out_hw_params()
[all …]
|
| /linux/drivers/phy/xilinx/ |
| H A D | phy-zynqmp.c | 30 * Lane Registers
163 /* Lane 0/1/2/3 offset */
174 /* Lane 0/1/2/3 Register */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
198 * struct xpsgtr_phy - representation of a lane
200 * @instance: instance of the protocol type (such as the lane within a
202 * @lane: lane number
203 * @protocol: protocol in which the lane operates
211 u8 lane; member
292 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_read_phy()
[all …]
|
| /linux/drivers/thunderbolt/ |
| H A D | lc.c | 100 u32 ctrl, lane; in tb_lc_set_port_configured() local
114 /* Resolve correct lane */ in tb_lc_set_port_configured()
116 lane = TB_LC_SX_CTRL_L1C; in tb_lc_set_port_configured()
118 lane = TB_LC_SX_CTRL_L2C; in tb_lc_set_port_configured()
121 ctrl |= lane; in tb_lc_set_port_configured()
125 ctrl &= ~lane; in tb_lc_set_port_configured()
162 u32 ctrl, lane; in tb_lc_set_xdomain_configured() local
176 /* Resolve correct lane */ in tb_lc_set_xdomain_configured()
178 lane = TB_LC_SX_CTRL_L1D; in tb_lc_set_xdomain_configured()
180 lane = TB_LC_SX_CTRL_L2D; in tb_lc_set_xdomain_configured()
[all …]
|
| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-pcie.c | 36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
40 * @lane_efuse_supported: software eFuse data is supported for this lane
51 * @num_lanes: supported lane numbers
67 * @efuse: pointer to eFuse data for each lane
81 unsigned int lane) in mtk_pcie_efuse_set_lane() argument
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
90 lane * PEXTP_ANA_LANE_OFFSET; in mtk_pcie_efuse_set_lane()
134 unsigned int lane) in mtk_pcie_efuse_read_for_lane() argument
136 struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_read_for_lane()
141 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane); in mtk_pcie_efuse_read_for_lane()
[all …]
|
| /linux/include/linux/phy/ |
| H A D | phy-mipi-dphy.h | 20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
42 * the transmitter prior to any associated Data Lane beginning
53 * Lane LP-00 Line state immediately before the HS-0 Line
65 * should ignore any Clock Lane HS transitions, starting from
76 * Time, in picoseconds, for the Clock Lane receiver to enable
105 * Time, in picoseconds, for the Data Lane receiver to enable
137 * Lane LP-00 Line state immediately before the HS-0 Line
149 * shall ignore any Data Lane HS transitions, starting from
161 * should ignore any transitions on the Data Lane, following a
[all …]
|
| /linux/drivers/media/platform/ti/omap3isp/ |
| H A D | omap3isp.h | 26 * @data_lane_shift: Data lane shifter
64 * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
65 * @pos: position of the lane
66 * @pol: polarity of the lane
77 * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
79 * @clk: Clock lane configuration
99 * @lanecfg: CCP2/CSI2 lane configuration
114 * @lanecfg: CSI-2 lane configuration
|
| /linux/drivers/net/ethernet/ti/ |
| H A D | netcp_xgbepcsr.c | 146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
182 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_enable() argument
184 /* Set Lane Control Rate */ in netcp_xgbe_serdes_lane_enable()
185 writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); in netcp_xgbe_serdes_lane_enable()
258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
[all …]
|
| /linux/Documentation/admin-guide/perf/ |
| H A D | dwc_pcie_pmu.rst | 20 events for a specified lane)
34 Lane Event counters
38 specific lane by the controller. The PMU event is selected by all of:
42 - Lane k
71 dwc_rootport_13018/rx_memory_read,lane=?/ [Kernel PMU event]
85 Lane Event Usage
88 Each lane has the same event set and to avoid generating a list of hundreds
89 of events, the user need to specify the lane ID explicitly, e.g.::
91 $# perf stat -a -e dwc_rootport_13018/rx_memory_read,lane=4/
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| /linux/drivers/ufs/host/ |
| H A D | ufs-qcom.c | 405 /* In case of single lane per direction, don't read lane1 clocks */ in ufs_qcom_check_hibern8()
633 * The PHY PLL output is the source of tx/rx lane symbol in ufs_qcom_fw_managed_hce_enable_notify()
634 * clocks, hence, enable the lane clocks only after PHY in ufs_qcom_fw_managed_hce_enable_notify()
971 int lane = max_t(u32, p->lane_rx, p->lane_tx); in ufs_qcom_set_tx_hs_equalizer()
978 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE, in ufs_qcom_set_tx_hs_equalizer()
979 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n", in ufs_qcom_set_tx_hs_equalizer()
980 lane, QCOM_UFS_MAX_LANE)) in ufs_qcom_set_tx_hs_equalizer()
981 lane = QCOM_UFS_MAX_LANE; in ufs_qcom_set_tx_hs_equalizer()
985 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; in ufs_qcom_set_tx_hs_equalizer()
940 int lane = max_t(u32, p->lane_rx, p->lane_tx); ufs_qcom_get_bw_table() local
2533 ufs_qcom_host_eom_config(struct ufs_hba * hba,int lane,const struct ufs_eom_coord * eom_coord,u32 target_test_count) ufs_qcom_host_eom_config() argument
2600 ufs_qcom_host_eom_may_stop(struct ufs_hba * hba,int lane,u32 target_test_count,u32 * err_count) ufs_qcom_host_eom_may_stop() argument
2661 int lane, ret; ufs_qcom_host_eom_scan() local
2726 int lane, i, ret; ufs_qcom_host_sw_rx_fom() local
2779 int lane, ret; ufs_qcom_get_rx_fom() local
2850 int lane; ufs_qcom_apply_tx_eqtr_settings() local
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | nvidia,tegra124-xusb-padctl.yaml | 15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
27 In addition to per-lane configuration, USB 3.0 ports may require additional
31 device tree node. Each lane exposed by the pad will be represented by its
32 own subnode and can be referenced by users of the lane using the standard
117 description: Function selection for this lane.
129 description: Function selection for this lane.
141 description: Function selection for this lane.
161 description: Function selection for this lane.
189 description: Function selection for this lane.
[all …]
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