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/linux/drivers/bus/
H A D	omap_l3_noc.c	3 * OMAP L3 Interconnect error handling driver 23 * @l3: pointer to l3 struct 35 * 1) Custom errors in L3 : 37 * 2) Standard L3 error: 39 * L3 tries to access target while it is idle 50 static int l3_handle_target(struct omap_l3 l3, void __iomem base, in l3_handle_target() argument 114 l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask); in l3_handle_target() 116 for (k = 0, master = l3->l3_masters; k < l3->num_masters; in l3_handle_target() 134 "%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n", in l3_handle_target() 135 dev_name(l3->dev), in l3_handle_target() [all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A D	qcom,osm-l3.yaml	`4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml# 7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider 13 L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM. 14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests 22 - qcom,sc7180-osm-l3 23 - qcom,sc8180x-osm-l3 24 - qcom,sdm670-osm-l3 25 - qcom,sdm845-osm-l3 26 - qcom,sm6350-osm-l3 27 - qcom,sm8150-osm-l3 [all …]`
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state", 48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state", 48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A D	datasource.json	20 …"BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 du… 160 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due t… 165 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a … 170 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due t… 175 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a … 180 …t dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss… 185 …t dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss… 190 …th data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss… 195 …th data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss… 200 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a … [all …]
/linux/arch/sparc/kernel/
H A D	head_64.S	`175 mov 1, %l3 176 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1 177 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 199 mov 4, %l3 200 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4 201 mov 1, %l3 202 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 206 mov 64, %l3 207 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size 214 mov (1b - prom_boot_mapped_pc), %l3 [all …]`
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A D	cache.json	5 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 6 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 11 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 12 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 65 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand … 66 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either o… 71 "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)", 77 …ssor's data cache was reloaded from a location other than the local core's L3 due to a demand load… 78 …ssor's data cache was reloaded from a location other than the local core's L3 due to either only d… 83 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co… [all …]
H A D	metrics.json	207 …escription": "Cycles stalled by GCT empty due to Icache misses that resolve in the local L2 or L3", 255 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where t… 261 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3", 267 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where t… 456 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst", 462 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst", 522 "BriefDescription": "% of DL1 reloads from Private L3 M state, other core per Inst", 528 "BriefDescription": "% of DL1 reloads from Private L3 S tate, other core per Inst", 534 …"BriefDescription": "Percentage of L3 load hits per instruction where the load collided with a pen… 540 "BriefDescription": "% of DL1 reloads from L3 per Inst", [all …]
H A D	marked.json	35 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 41 …ation in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node … 47 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 53 …uration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node … 155 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked … 161 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load… 167 … "Duration in cycles to reload from a location other than the local core's L3 due to a marked load… 173 "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load", 179 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co… 185 …"BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due … [all …]
H A D	frontend.json	89 …uction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 90 …uction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 95 …truction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 96 …truction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 149 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an… 150 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to e… 156 "PublicDescription": "Inst from L3 miss" 161 …Instruction cache was reloaded from a location other than the local core's L3 due to a instruction… 162 …Instruction cache was reloaded from a location other than the local core's L3 due to either an ins… 167 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with disp… [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	memory.json	3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 12 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 204 "BriefDescription": "Demand Data Read requests who miss L3 cache", 208 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 213 …"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the sup… 222 … "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ … 230 …"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the su… 239 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", 249 …"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified dat… 259 …"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared … [all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 39 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s… 48 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.… 57 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.… 66 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-sta… 75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", 84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", [all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 39 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s… 48 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.… 57 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.… 66 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-sta… 75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", 84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 39 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s… 48 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.… 57 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.… 66 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-sta… 75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", 84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A D	other.json	35 "BriefDescription": "L3 initiated LCO received retry on port 2 (can try 4 times)" 45 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load" 50 …try was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due… 120 …"BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to … 160 "BriefDescription": "L3 PF from Off chip memory" 190 …"BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modifie… 205 …uration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due… 235 … "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated" 245 "BriefDescription": "L3 PF sent with nodal scope port 1, counts even retried requests" 260 "BriefDescription": "L3 CO received retry port 3 (memory only), every retry counted" [all …]
H A D	marked.json	10 …ory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The sour… 20 …ble Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due… 50 …Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This imp… 70 …Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due… 85 …Instruction cache was reloaded from a location other than the local core's L3 due to a instruction… 95 …try was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due… 100 …Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due… 110 … "Duration in cycles to reload from a location other than the local core's L3 due to a marked load" 180 …ocessor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due… 185 …essor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due… [all …]
H A D	metrics.json	80 …iefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)", 86 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl… 92 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 without conf… 98 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3", 104 "BriefDescription": "Completion stall due to cache miss resolving missed the L3", 271 …n Completion Table empty for this thread due to icache misses that were sourced from the local L3", 277 …r this thread due to icache misses that were sourced from beyond the local L3. The source could be… 601 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst", 607 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst", 643 "BriefDescription": "% of DL1 reloads from Private L3 M state, other core per Inst", [all …]
/linux/Documentation/devicetree/bindings/arm/omap/
H A D	l3-noc.txt	`1 * TI - L3 Network On Chip (NoC) 7 - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family 8 Should be "ti,omap4-l3-noc" for OMAP4 family 9 Should be "ti,omap5-l3-noc" for OMAP5 family 10 Should be "ti,dra7-l3-noc" for DRA7 family 11 Should be "ti,am4372-l3-noc" for AM43 family 12 - reg: Contains L3 register address range for each noc domain. 18 compatible = "ti,omap4-l3-noc", "simple-bus";`
/linux/tools/testing/selftests/drivers/net/netdevsim/
H A D	hw_stats_l3.sh	`242 reporting_test l3 291 fail_next_test l3 318 local pkts=$(get_hwstat dummy1 l3 rx.packets) 324 local pkts=$(get_hwstat dummy1 l3 rx.packets) 333 local pkts=$(get_hwstat dummy1 l3 rx.packets) 345 local pkts=$(get_hwstat dummy1 l3 rx.packets) 356 counter_test l3 365 nsim_hwstats_enable 1 dummy1 l3 366 nsim_hwstats_enable 2 dummy1 l3 367 nsim_hwstats_enable 3 dummy1 l3 [all …]`
/linux/Documentation/devicetree/bindings/regulator/
H A D	qcom,smd-rpm-regulator.yaml	27 For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, 30 For pm6125 s1, s2, s3, s4, s5, s6, s7, s8, l1, l2, l3, l5, l6, l7, l8, l9, 33 For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22, 36 For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob 38 For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, 44 For pm8909, s1, s2, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, 47 For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, 50 For pm8937, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, 53 For pm8941, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, 57 For pm8950 and pm8953, s1, s2, s3, s4, s5, s6, s7, l1, l2, l3, l4, l5, l6, [all …]
/linux/drivers/gpu/drm/xe/
H A D	xe_mocs.c	`94 /* L3 caching options / 140 NOTE2: Reserved and unspecified MOCS indices have been set to L3 WB. These 146 /* Base - L3 + LLC / 154 / Base - L3 / 166 / Age 0 - L3 + LLC / 174 / Age: Don't Chg. - L3 + LLC / 182 / No AOM - L3 + LLC / 190 / No AOM; Age 0 - L3 + LLC / 198 / No AOM; Age:DC - L3 + LLC / 202 / Self-Snoop - L3 + LLC */ [all …]`
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	memory.json	201 "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", 211 …"BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned … 221 "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", 231 …"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned … 241 …"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned … 251 …"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is … 261 …"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data … 271 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", 281 …"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data i… 291 …"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data i… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A D	cache.json	29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.", 77 "BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.", 83 …"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in… 197 …"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the… 245 …"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the… 502 …fetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stre… 508 …fetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Next… 514 …fetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2UpDo… 520 …fetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Burs… 526 …fetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stri… [all …]
/linux/drivers/clk/ti/
H A D	clk-44xx.c	323 { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" }, 339 { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" }, 375 "l3-init-clkctrl:0038:24", 380 "l3-init-clkctrl:0038:25", 421 "l3-init-clkctrl:0040:24", 455 { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" }, 456 { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" }, 457 { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" }, 462 …{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c… 728 DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"), [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A D	extended.json	111 "BriefDescription": "L1D On-Chip L3 Sourced Writes", 118 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", 132 "BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention", 139 "BriefDescription": "L1D On-Node L3 Sourced Writes", 153 "BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention", 160 "BriefDescription": "L1D On-Drawer L3 Sourced Writes", 174 "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention", 181 "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes", 188 "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes", 195 "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention", [all …]

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