Home
last modified time | relevance | path

Searched +full:l2 +full:- +full:tag +full:- +full:latency (Results 1 – 25 of 35) sorted by relevance

12

/linux/Documentation/devicetree/bindings/cache/
H A Dbaikal,bt1-l2-ctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 L2-cache Control Block
11 - Serge Semin <fancer.lancer@gmail.com>
14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17 L2-cache controller block is responsible for the tuning. Its DT node is
[all …]
/linux/drivers/memory/
H A Dbt1-l2-ctl.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
40 * @sys_regs: Baikal-T1 System Controller registers map.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
50 * @L2_WSSTALL: Way-select latency.
51 * @L2_TAGSTALL: Tag latency.
52 * @L2_DATASTALL: Data latency.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 { label
13 compatible = "arm,pl310-cache";
15 cache-unified;
16 cache-level = <2>;
17 arm,data-latency = <3 3 3>;
18 arm,tag-latency = <2 2 2>;
/linux/arch/x86/include/asm/
H A Damd-ibs.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include <asm/msr-index.h>
33 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
34 fetch_cnt:16, /* 16-31: instruction fetch count */
35 fetch_lat:16, /* 32-47: instruction fetch latency */
39 ic_miss:1, /* 51: i-cache miss */
41 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size
43 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */
44 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */
[all …]
/linux/tools/arch/x86/include/asm/
H A Damd-ibs.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include "msr-index.h"
33 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
34 fetch_cnt:16, /* 16-31: instruction fetch count */
35 fetch_lat:16, /* 32-47: instruction fetch latency */
39 ic_miss:1, /* 51: i-cache miss */
41 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size
43 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */
44 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */
[all …]
/linux/arch/arm/mm/
H A Dcache-l2x0.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support
20 #include <asm/hardware/cache-l2x0.h>
21 #include <asm/hardware/cache-aurora-l2.h>
22 #include "cache-tauros3.h"
63 * override this if they are running non-secure.
77 * register be written due to a work-around, as platforms running
78 * in non-secure mode may not be able to access this register.
109 * Enable the L2 cache controller. This function must only be
119 l2x0_data->configure(base); in l2c_enable()
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Dcache.json5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
10 …Description": "The number of 32B fetch windows tried to read the L1 IC and missed in the full tag."
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 …ting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cro…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
[all …]
/linux/arch/arm/boot/dts/arm/
H A Darm-realview-pbx-a9.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
[all …]
H A Dvexpress-v2p-ca9.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A9 MPCore (V2P-CA9)
8 * HBI-0191B
11 /dts-v1/;
12 #include "vexpress-v2m.dtsi"
15 model = "V2P-CA9";
18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2q.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
[all …]
/linux/Documentation/networking/dsa/
H A Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
[all …]
/linux/Documentation/networking/
H A Dbridge.rst1 .. SPDX-License-Identifier: GPL-2.0
10 The IEEE 802.1Q-2022 (Bridges and Bridged Networks) standard defines the
23 .. kernel-doc:: net/bridge/br_private.h
33 -------------------------
35 .. kernel-doc:: include/uapi/linux/if_link.h
39 ------------------------------
41 .. kernel-doc:: include/uapi/linux/if_link.h
45 ------------
62 <https://lore.kernel.org/netdev/20220316150857.2442916-1-tobias@waldekranz.com/>`_.
64 The 802.1D-2004 removed the original Spanning Tree Protocol, instead
[all …]
/linux/arch/arm/boot/dts/actions/
H A Dowl-s500.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (c) 2016-2017 Andreas Färber
8 #include <dt-bindings/clock/actions,s500-cmu.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/owl-s500-powergate.h>
12 #include <dt-bindings/reset/actions,s500-reset.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Diavf.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2013-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Additional Configurations
16 - Known Issues/Troubleshooting
17 - Support
30 The guest OS loading the iavf driver must support MSI-X interrupts.
53 ---------------------
58 # dmesg -n 8
[all …]
/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v1.0
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
16 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
35 1, 0, ecx, 2, dtes64 , 64-bit DS save area
49 1, 0, ecx, 17, pcid , Process-context identifiers
56 1, 0, ecx, 24, tsc_deadline_timer , APIC timer one-shot operation
[all …]
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
[all …]
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7740.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/linux/arch/mips/kernel/
H A Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
80 /* ZSC L2 Cache Register Access Register Definitions */
112 * Description: compute the I-cache size and I-cache line size
131 * vi) 0x5 - 0x7: Reserved.
146 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
174 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
175 * 4-way, v) 0x4 - 0x7: Reserved.
207 * Description: compute the D-cache size and D-cache line size.
224 * vi) 0x5 - 0x7: Reserved.
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
18 L2: cache-controller { label
19 compatible = "arm,l210-cache";
21 interrupt-parent = <&vica>;
23 cache-unified;
24 cache-level = <2>;
[all …]
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
[all …]
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_txrx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
25 * iavf_unmap_and_free_tx_resource - Release a Tx buffer
32 if (tx_buffer->skb) { in iavf_unmap_and_free_tx_resource()
33 if (tx_buffer->tx_flags & IAVF_TX_FLAGS_FD_SB) in iavf_unmap_and_free_tx_resource()
34 kfree(tx_buffer->raw_buf); in iavf_unmap_and_free_tx_resource()
36 dev_kfree_skb_any(tx_buffer->skb); in iavf_unmap_and_free_tx_resource()
38 dma_unmap_single(ring->dev, in iavf_unmap_and_free_tx_resource()
43 dma_unmap_page(ring->dev, in iavf_unmap_and_free_tx_resource()
49 tx_buffer->next_to_watch = NULL; in iavf_unmap_and_free_tx_resource()
[all …]
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_txrx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
16 * i40e_fdir - Generate a Flow Director descriptor based on fdata
26 struct i40e_pf *pf = tx_ring->vsi->back; in i40e_fdir()
31 i = tx_ring->next_to_use; in i40e_fdir()
35 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; in i40e_fdir()
37 flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK, fdata->q_index); in i40e_fdir()
40 fdata->flex_off); in i40e_fdir()
42 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_PCTYPE_MASK, fdata->pctype); in i40e_fdir()
45 vsi_id = fdata->dest_vsi ? : i40e_pf_get_main_vsi(pf)->id; in i40e_fdir()
[all …]

12