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/linux/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
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H A Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
19 - if:
24 - ethernet-phy-id004d.d0c0
33 - description:
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/linux/drivers/clk/at91/
H A Dsam9x7.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/at91.h>
23 * enum pll_ids - PLL clocks identifiers
26 * @PLL_ID_AUDIO: Audio PLL identifier
27 * @PLL_ID_LVDS: LVDS PLL identifier
29 * @PLL_ID_MAX: Max PLL Identifier
41 * enum pll_type - PLL type identifiers
42 * @PLL_TYPE_FRAC: fractional PLL identifier
43 * @PLL_TYPE_DIV: divider PLL identifier
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H A Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
33 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
53 "atmel,sama5d2-clk-audio-pll-frac",
59 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
79 "atmel,sama5d2-clk-audio-pll-pad",
85 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
105 "atmel,sama5d2-clk-audio-pll-pmc",
161 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
162 name = gcknp->name; in of_sama5d2_clk_generated_setup()
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H A Dsam9x60.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
6 #include <dt-bindings/clock/at91.h>
29 /* Fractional PLL core output range. */
91 * ddrck feeds DDR controller and is enabled by bootloader thus we need
92 * to keep it enabled in case there is no Linux consumer for it.
151 * mpddr_clk feeds DDR controller and is enabled by bootloader thus we
152 * need to keep it enabled in case there is no Linux consumer for it.
198 i = of_property_match_string(np, "clock-names", "td_slck"); in sam9x60_pmc_setup()
204 i = of_property_match_string(np, "clock-names", "md_slck"); in sam9x60_pmc_setup()
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3328-orangepi-r1-plus-lts.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
9 /dts-v1/;
11 #include "rk3328-orangepi-r1-plus.dtsi"
15 compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
19 phy-handle = <&yt8531c>;
20 phy-mode = "rgmii-id";
24 yt8531c: ethernet-phy@0 {
25 compatible = "ethernet-phy-ieee802.3-c22";
28 motorcomm,auto-sleep-disabled;
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28-var4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
12 /dts-v1/;
13 #include "fsl-ls1028a-kontron-sl28.dts"
14 #include <dt-bindings/net/qca-ar803x.h>
17 model = "Kontron SMARC-sAL28 (Dual PHY)";
18 compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
22 phy1: ethernet-phy@4 {
24 eee-broken-1000t;
25 eee-broken-100tx;
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H A Dfsl-ls1028a-kontron-sl28-var1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
15 /dts-v1/;
16 #include "fsl-ls1028a-kontron-sl28.dts"
17 #include <dt-bindings/net/qca-ar803x.h>
20 model = "Kontron SMARC-sAL28 (4 Lanes)";
21 compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
26 /delete-node/ ethernet-phy@5;
28 phy0: ethernet-phy@4 {
30 eee-broken-1000t;
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/linux/Documentation/devicetree/bindings/net/dsa/
H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
28 - qca,qca8327
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_legacy_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
40 struct drm_device *dev = crtc->dev; in radeon_overscan_setup()
41 struct radeon_device *rdev = dev->dev_private; in radeon_overscan_setup()
44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
52 struct drm_device *dev = crtc->dev; in radeon_legacy_rmx_mode_set()
53 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_rmx_mode_set()
55 int xres = mode->hdisplay; in radeon_legacy_rmx_mode_set()
56 int yres = mode->vdisplay; in radeon_legacy_rmx_mode_set()
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/linux/drivers/clk/samsung/
H A Dclk-exynos-arm64.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "clk-exynos-arm64.h"
20 /* PLL register bits */
67 * exynos_arm64_init_clocks - Set clocks initial configuration
71 * Set manual control mode for all gate and PLL clocks.
76 const unsigned long *reg_offs = cmu->clk_regs; in exynos_arm64_init_clocks()
77 size_t reg_offs_len = cmu->nr_clk_regs; in exynos_arm64_init_clocks()
89 if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) { in exynos_arm64_init_clocks()
103 * exynos_arm64_enable_bus_clk - Enable parent clock of specified CMU
110 * Keep CMU parent clock running (needed for CMU registers access).
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/linux/include/linux/habanalabs/
H A Dhl_boot_if.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2018-2023 HabanaLabs, Ltd.
11 #define LKD_HARD_RESET_MAGIC 0xED7BD694 /* deprecated - do not use */
47 * will clear the non-relevant ones.
67 * Boot continues as usual, but keep in
89 * started, but is not ready yet - chip
114 * CPU_BOOT_ERR0_PLL_FAIL PLL settings failed, meaning that one
139 * CPU_BOOT_ERR0_ENABLED Error registers enabled.
206 * CPU_BOOT_DEV_STS0_SECURITY_EN Security is Enabled.
208 * enabled in FW, which means that
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/linux/drivers/clk/st/
H A Dclkgen-fsyn.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
20 * Maximum input clock to the PLL before we divide it down by 2
129 { .name = "clk-s-c0-fs0-ch0", },
130 { .name = "clk-s-c0-fs0-ch1", },
131 { .name = "clk-s-c0-fs0-ch2", },
132 { .name = "clk-s-c0-fs0-ch3", },
186 { .name = "clk-s-d0-fs0-ch0", },
187 { .name = "clk-s-d0-fs0-ch1", },
188 { .name = "clk-s-d0-fs0-ch2", },
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/linux/drivers/net/wireless/broadcom/b43/
H A Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
212 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
234 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
235 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
330 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
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/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ------------
31 ----------------------------
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
47 "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical
49 "63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance
51 "5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call
53 "9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2
55 "F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Boss
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/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
34 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
49 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
103 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
105 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
154 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
156 #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
157 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
235 #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled…
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/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
25 /* helpers to keep the MCLK intermediates "somewhere" in our table */
88 * NFC IP block, output clocks, system PLL status query, different CPMF
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
292 val &= (1 << len) - 1; in get_bit_field()
296 /* get the SPMF and translate it into the "sys pll" multiplier */
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
41 * since the registers are 16-bit.
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
301 /*-----------------------------------------------------------*/
392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
400 if (lane->id == 2) { in comphy_lane_reg_set()
402 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
406 void __iomem *base = lane->id == 1 ? in comphy_lane_reg_set()
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/linux/include/linux/ssb/
H A Dssb_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
37 #define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
161 …e SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
163 …CLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable reque…
260 /** PMU PLL registers */
262 /* PMU rev 0 PLL registers */
276 /* PMU rev 1 PLL registers */
308 /* BCM4312 PLL resource numbers. */
[all …]
/linux/drivers/pmdomain/imx/
H A Dscu-pd.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
10 * single global power domain and implement the ->attach|detach_dev()
12 * From within the ->attach_dev(), we could get the OF node for
13 * the device that is being attached and then parse the power-domain
18 * Additionally, we need to implement the ->stop() and ->start()
20 * rather than using the above ->power_on|off() callbacks.
23 * 1. The ->attach_dev() of power domain infrastructure still does
32 * Update: Genpd assigns the ->of_node for the virtual device before it
33 * invokes ->attach_dev() callback, hence parsing for device resources via
[all …]
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Db43legacy.h1 /* SPDX-License-Identifier: GPL-2.0 */
59 /* 32-bit DMA */
66 /* 64-bit DMA */
119 #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */
120 #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */
153 #define B43legacy_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
154 #define B43legacy_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
163 #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
164 #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */
192 #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
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/linux/drivers/i2c/busses/
H A Di2c-mlxbf.c1 // SPDX-License-Identifier: GPL-2.0
57 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
59 * memory-mapped region whose addresses are specified in either the DT or
69 /* Reference clock for Bluefield - 156 MHz. */
72 /* Constant used to determine the PLL frequency. */
77 /* PLL registers. */
90 * as interrupt enabled bits.
127 * as interrupt enabled bits.
151 * SMBUS GW0 -> bits[26:25]
152 * SMBUS GW1 -> bits[28:27]
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/linux/drivers/usb/host/
H A Dehci-pci.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2000-2004 by David Brownell
15 #include "pci-quirks.h"
19 static const char hcd_name[] = "ehci-pci";
27 /*-------------------------------------------------------------------------*/
31 return pdev->vendor == PCI_VENDOR_ID_INTEL && in is_intel_quark_x1000()
32 pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC; in is_intel_quark_x1000()
62 /* called after powerup, by probe or system-pm "wakeup" */
71 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ in ehci_pci_reinit()
83 ehci->regs->intel_quark_x1000_insnreg01); in ehci_pci_reinit()
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/linux/drivers/net/ethernet/sun/
H A Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
130 * This 13-bit register is programmed by the driver to hold the descriptor
136 * This 13-bit register is updated by GEM to hold to descriptor entry index
171 * them later. -DaveM
220 #define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */
221 #define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */
222 #define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */
223 #define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */
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/linux/sound/soc/codecs/
H A Dda7219-aad.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * da7219-aad.c - Dialog DA7219 ALSA SoC AAD Driver
24 #include "da7219-aad.h"
35 da7219->aad->jack = jack; in da7219_aad_jack_det()
36 da7219->aad->jack_inserted = false; in da7219_aad_jack_det()
55 struct snd_soc_component *component = da7219_aad->component; in da7219_aad_btn_det_work()
83 dev_warn(component->dev, "Mic bias status check timed out"); in da7219_aad_btn_det_work()
85 da7219->micbias_on_event = true; in da7219_aad_btn_det_work()
91 if (da7219_aad->micbias_pulse_lvl && da7219_aad->micbias_pulse_time) { in da7219_aad_btn_det_work()
96 da7219_aad->micbias_pulse_lvl); in da7219_aad_btn_det_work()
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