Lines Matching +full:keep +full:- +full:pll +full:- +full:enabled

1 .. SPDX-License-Identifier: GPL-2.0
12 ------------
31 ----------------------------
43 	"42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 	"3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
47 	"97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical
49 	"63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance
51 	"5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call
53 	"9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2
55 	"F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Boss
57 	"6ED722A7-9240-48A5-B479-31EEF723D7CF" : Virtual Sensor
59 	"16CAF1B7-DD38-40ED-B1C1-1B8A1913D531" : Cooling mode
61 	"BE84BABF-C4D4-403D-B495-3128FD44dAC1" : HDC
72 	for sending keep alive notification. User space receives
92 ------------------------------------------
118 -------------------------
124 --------------------------
130 --------------------------------------------
219 single user-level manager owns and manages the controls. If multiple
220 user-level software applications attempt to write different targets, it
225 --------------------------------------------
233 with very sensitive wireless receivers such as Wi-Fi and cellular that
255 DDR-RFIM) for Wi-Fi from BIOS.
263 	The VCO reference code is an 11-bit field and controls the FIVR
264 	switching frequency. This is the 3-bit LSB field.
267 	The VCO reference code is an 11-bit field and controls the FIVR
268 	switching frequency. This is the 8-bit MSB field.
325 	Current DLVR PLL frequency in MHz.
328 	Sets DLVR PLL clock frequency. Once set, and enabled via
330 	DLVR PLL frequency.
333 	PLL can't accept frequency change when set.
350 ----------------------------------------
352 Refer to Documentation/ABI/testing/sysfs-platform-dptf
355 ----------------------------------------
357 Refer to Documentation/admin-guide/acpi/fan_performance_states.rst
360 ----------------------------------------
394 	0 -  Idle: System performs no tasks, power and idle residency are